KM681002B Ver la hoja de datos (PDF) - Samsung
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KM681002B Datasheet PDF : 8 Pages
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KM681002B, KM681002BI
PRELIMINARY
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CMOS SRAM
128K x 8 Bit High-Speed CMOS Static RAM
FEATURES
• Fast Access Time 8,10,12ns(Max.)
• Low Power Dissipation
Standby (TTL) : 50 mA(Max.)
(CMOS) : 10 mA(Max.)
Operating KM681002B - 8 : 160 mA(Max.)
KM681002B - 10 : 155 mA(Max.)
KM681002B - 12 : 150 mA(Max.)
• Single 5.0V ±10% Power Supply
• TTL Compatible Inputs and Outputs
• I/O Compatible with 3.3V Device
• Fully Static Operation
- No Clock or Refresh required
• Three State Outputs
• Center Power/Ground Pin Configuration
• Standard Pin Configuration
KM681002BJ : 32-SOJ-400
KM681002BT: 32-TSOP2-400F
GENERAL DESCRIPTION
The KM681002B is a 1,048,576-bit high-speed Static Random
Access Memory organized as 131,072 words by 8 bits. The
KM681002B uses 8 common input and output lines and has an
output enable pin which operates faster than address access
time at read cycle. The device is fabricated using Samsung ′s
advanced CMOS process and designed for high-speed circuit
technology. It is particularly well suited for use in high-density
high-speed system applications. The KM681002B is packaged
in a 400mil 32-pin plastic SOJ or TSOP2 forward.
ORDERING INFORMATION
KM681002B -8/10/12
KM681002BI -8/10/12
Commercial Temp.
Industrial Temp.
PIN CONFIGURATION (Top View)
FUNCTIONAL BLOCK DIAGRAM
Clk Gen.
Pre-Charge Circuit
A0
A1
A2
A3
Memory Array
A4
256 Rows
512x8 Columns
A5
A6
A7
I/O1~I/O8
Data
Cont.
I/O Circuit
Column Select
CLK
Gen.
A8 A9 A10 A11 A12 A13 A14 A15 A16
CS
WE
OE
A0 1
A1 2
A2 3
A3 4
CS 5
I/O1 6
I/O2 7
Vcc 8
Vss 9
I/O3 10
I/O4 11
WE 12
A4 13
A5 14
A6 15
A7 16
SOJ/
TSOP2
32 A16
31 A15
30 A14
29 A13
28 OE
27 I/O8
26 I/O7
25 Vss
24 Vcc
23 I/O6
22 I/O5
21 A12
20 A11
19 A10
18 A9
17 A8
PIN FUNCTION
Pin Name
A0 - A16
WE
CS
OE
I/O1 ~ I/O8
VCC
VSS
N.C
Pin Function
Address Inputs
Write Enable
Chip Select
Output Enable
Data Inputs/Outputs
Power(+5.0V)
Ground
No Connection
-2-
Rev 2.0
February 1998
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