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KB2512

DEFLECTION PROCESSOR FOR MULTISYNC MONITORS

Samsung 

DEFLECTION PROCESSOR FOR MULTISYNC MONITORS

KB2512

I2C Control Adjustments

Then, S and C correction shapes can be added to this ramp. This frequency independent S and C corrections are

generated internally. Their amplitude are adjustable by their respective I2C register. They can also be inhibited by

their select bit. The amplitude of this S and C corrected ramp can be adjusted by the vertical ramp amplitude

control register. The adjusted ramp is available on pin 23 (VOUT) to drive an external power stage. The gain of this

stage is typically 25% depending on its register value. The mean value of this ramp is driven by its own I2C register

(vertical position). Its value is VPOS = 7/16 • VREF ± 300mV.

Usually VOUT is sent through a resistive divider to the inverting input of the booster. Since VPOS derives from

VREF-V, the bias voltage sent to the non-inverting input of booster should also derive from VREF-V to optimize the

accuracy (see application diagram).

Basic Equations

In first approximation, the amplitude of the ramp on pin 23 (Vout) is:

VOUT - VPOS = (VOSC - VDCMID) • (1 + 0.25 (VAMP) )

with:

• VDCMID = 7/16•VREF (typically 3.5V, the middle value of the ramp on pin 22)

• VOSC = V22 (ramp with fixed amplitude)

• VAMP = - 1 for minimum vertical amplitude register value and +1 for maximum

• VPOS is calculated by: VPOS = VDCMID + 0.3Vp with Vp equals -1 for minimum vertical position register value

and +1 for maximum

The current available on pin 22 is:

IOSC

=

3

8

• VREF • COSC • f

with COSC: capacitor connected on pin 22

f: synchronization frequency.

Vertical Moire

By using the vertical moire, VPOS can be modulated from frame to frame. This function is intended to cancel the

fringes which appear when line to line interval is very close to the CRT vertical pitch. The amplitude of the

modulation is controlled by register VMOIRE on address OC and can be switched - off via the control bit D7.

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