KA3882CDTF Ver la hoja de datos (PDF) - Fairchild Semiconductor
Número de pieza
componentes Descripción
Fabricante
KA3882CDTF Datasheet PDF : 6 Pages
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KA3882C/KA3883C
Electrical Characteristics (Continued)
(VCC = 15V, RT = 10kΩ, CT = 3.3nF, TA = 0°C to +70°C, Unless otherwise specified)
Parameter
Symbol
Conditions
ERROR AMPLIFIER SECTION
Input Voltage
VI
TPIN1 = 2.5V
Input Bias Current
IBIAS
-
Open Loop Gain
GVO VO = 2V to 4V (Note1)
Unity Gain Bandwidth
GBW TJ= 25°C (Note1)
PSRR
PSRR VCC = 12V to 25V (Note1)
Output Sink Current
ISINK VPIN2 = 2.7V, VPIN1 = 1.1V
Output Source Current
ISOURCE VPIN2 = 2.3V, VPIN1 = 5.0V
Output High Voltage
Output Low Voltage
VOH
VOL
VPIN2 = 2.3V, R1 = 15kΩ to GND
VPIN2 = 2.7V, R1 = 15kΩ to Pin8
OUTPUT SECTION
Output Low Level
VOL
ISINK = 20mA
ISINK = 200mA
Output High Level
VOH
ISOURCE = 20mA
ISOURCE = 200mA
Rise Time
tR
TJ = 25°C, C1 = 1nF (Note1)
Fall Time
tF
TJ = 25°C, C1 = 1nF (Note1)
Output Voltage Swing Limit
VOLIM VCC = 27V, C1 = 1nF
UNDER VOLTAGE LOCKOUT SECTION
Start Threshold
KA3882C
VTH
KA3883C
Min. Operating Voltage
( After turn on )
KA3882C
VTL
KA3883C
PWM SECTION
Maximum Duty Cycle
DMAX KA3882C/KA3883C
Minimum Duty Cycle
DMIN
-
TOTAL STANDBY CURRENT
Start-Up Current
IST
-
Operating Supply Current
ICC
VPIN2 = VPIN3 = 0V
VCC Zener Voltage
VZ
ICC = 25mA
Min. Typ. Max. Unit
2.42 2.50 2.58 V
- -0.3 -2 uA
65 90
-
dB
0.7 1
- MHz
60 70
-
dB
2
6
- mA
-0.5 -0.8 - mA
5
6
-
V
- 0.8 1.1 V
- 0.1 0.4 V
- 1.5 2.2 V
13 13.5 -
V
12 13.5 -
V
-
40 100 ns
-
40 100 ns
-
22
-
V
15 16 17 V
7.8 8.4 9.0 V
9 10 11 V
7.0 7.6 8.2 V
94 96 100 %
-
-
0
%
- 0.2 0.4 mA
-
11 17 mA
-
29
-
V
* Adjust VCC above the start threshold before setting at 15V
Notes :
1. These parameters, although guaranteed, are not 100% tested in production.
2. Parameter measured at trip point of latch with V2 = 0V.
3. Gain defined as: GV = ∆VPIN1∆VPIN3(VPIN3 = 0 to 0.8V)
4. Junction-to-air thermal resistance test enviroments.
-. PCB information ;
Board thickness : 1.6mm , Board dimension : 76.2 X 114.3mm2 , Ref. : EIA / JSED51-3 and EIA / JSED51-7
-. Board structure; Using the single layer PCB.
3
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