MK53X256CLQ100 Ver la hoja de datos (PDF) - Freescale Semiconductor

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MK53X256CLQ100

K53 Sub-Family Data Sheet

Freescale Semiconductor 

General

5. 25MHz core and system clock, 25MHz bus clock, and 12.5MHz FlexBus and flash clock. MCG configured for FEI mode.

6. 2 MHz core, system, FlexBus, and bus clock and 1MHz flash clock. MCG configured for fast IRCLK mode. All peripheral

clocks disabled. Code executing from flash.

7. 2 MHz core, system, FlexBus, and bus clock and 1MHz flash clock. MCG configured for fast IRCLK mode. All peripheral

clocks enabled but peripherals are not in active operation. Code executing from flash.

8. 2 MHz core, system, FlexBus, and bus clock and 1MHz flash clock. MCG configured for fast IRCLK mode. All peripheral

clocks disabled.

9. Includes 32kHz oscillator current and RTC operation.

5.1.5.1 Diagram: Typical IDD_RUN operating behavior

The following data was measured under these conditions:

• MCG in FEI mode (39.0625 kHz IRC), except for 1 MHz core (FBE)

• All peripheral clocks disabled except FTFL

• LVD disabled, USB regulator disabled

• No GPIOs toggled

• Code execution from flash

Figure 1. Run mode supply current vs. core frequency — all peripheral clocks disabled

The following data was measured under these conditions:

K53 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.

Freescale Semiconductor, Inc.

Preliminary

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