HDLR-2416 Ver la hoja de datos (PDF) - HP => Agilent Technologies

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HDLR-2416

Four Character 5.0 mm (0.2 inch) Smart 5 x 7 Alphanumeric Displays

HP => Agilent Technologies 

10

strobing the blank input). All of

these blanking modes affect only

the output drivers, maintaining the

contents and write capability of

the internal RAMs and Control

Register, so that normal loading of

RAMs and Control Register can

take place even with the display

blanked.

Figure 3 shows how the Extended

Function Disable (bit D6 of the

Control Register), Master Blank

(bit D2 of the Control Register),

Digit Blank Disable (bit D1 of the

Attribute RAM), and BL input can

be used to blank the display.

EFD MB DBDn BL

0

0

0

0 Display Blanked by BL

0

0

X

1 Display ON

0

X

1

0

Display Blanked by BL. Individual characters

"ON" based on "1" being stored in DBDn

0

1

0

X Display Blanked by MB

0

1

1

1

Display Blanked by MB. Individual characters

"ON" based on "1" being stored in DBDn

1

X

X

0 Display Blanked by BL

1

X

X

1 Display ON

When the Extended Function

Disable is a logic 1, the display

can be blanked only with the BL

input. When the Extended

Function Disable is a logic 0, the

display can be blanked through

the BL input, the Master Blank,

and the Digit Blank Disable. The

entire display will be blanked if

either the BL input is logic 0 or

the Master Blank is logic 1,

providing all Digit Blank Disable

bits are logic 0. Those digits with

Digit Blank Disable bits a logic 1

will ignore both blank signals and

remain ON. The Digit Blank

Disable bits allow individual

characters to be blanked or

flashed in synchronization with the

BL input.

Figure 3. Display Blanking Truth Table

Dimming

Dimming of the display is con-

trolled through either the BL input

or the Control Register. A pulse

width modulated signal can be

applied to the BL input to dim the

display. A three bit word in the

Control Register generates an

internal pulse width modulated

signal to dim the display. The

internal dimming feature is

enabled only if the Extended

Function Disable is a logic 0.

Bits 3-5 in the Control Register

provide internal brightness

control. These bits are interpreted

as a three bit binary code, with

code (000) corresponding to the

maximum brightness and code

(111) to the minimum brightness.

In addition to varying the display

brightness, bits 3-5 also vary the

average value of IDD. IDD can be

specified at any brightness level as

shown in Table 1.

Table 1. Current Requirements at Different Brightness Levels

Symbol

IDD(#)

D5 D4 D3

00 0

00 1

Brightness

100%

60%

25°C Typ.

110

66

25°C Max.

130

79

01 0

40%

45

53

01 1

27%

30

37

10 0

17%

20

24

10 1

10%

12

15

11 0

7%

9

11

11 1

3%

4

6

Max. over Temp.

160

98

66

46

31

20

15

9

Units

mA

mA

mA

mA

mA

mA

mA

mA

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