IXTA200N055T2 Ver la hoja de datos (PDF) - IXYS CORPORATION
Número de pieza
componentes Descripción
Fabricante
IXTA200N055T2 Datasheet PDF : 11 Pages
| |||
DC to DC Synchronous Converter Design
Abdus Sattar, IXYS Corporation
IXAN0068
Design Example 1:
Assume design parameters as VIN=12V, VO=3.3V and Io=12A.
Table 1: Design Consideration 1 for synchronous buck converter
Input Voltage, Vin
12V
Output Voltage, Vo
3.3V
Output Current, Io
12A
Assume the output ripple voltage is within ± 1% of Vo. For Vo =3.3V, the output ripple
is limited within, ΔVL (t) ≤ 0.033V . When the output capacitor (C1) is 10uF, the inductor
L1 values for the range of switching frequencies from 100 kHz to 500 kHz are given in
Table: 2 based on equations 3-7.
Table 2: When C1= 10uF
Vin Vo
(V) (V) D
ΔVL fs
(V) (kHz)
12 3.3 0.275 0.033
100
12 3.3 0.275 0.033
200
12 3.3 0.275 0.033
300
12 3.3 0.275 0.033
400
12 3.3 0.275 0.033
500
C1
(uF)
10
10
10
10
10
ΔΙL1
(A)
0.264
0.528
0.792
1.056
1.32
L1
(uH)
90
45.31
30.20
22.65
18.12
fc
(kHz)
5.31
7.48
9.16
10.60
11.83
Synchronous Driver Controller: ISL6594D from Intersil:
Based on equation 18 and 19, From ISL6594D driver datasheet, given high-side: tr=26nS,
tf=18nS and source/sink current = 1.25/2A (max). For low-side, trr=18nS, tf=12nS and
source/sink current = 2/3.0 A (max):
Table 4: from Datasheet
High-Side Rise time Source Current (A) Required Qg(on)
Source
Sink
Low-Side
26 ns
18 ns
Rise time
1.25
2
Source Current (A)
32.5nC
36nC
Required Qg(on)
Source
Sink
18nS
2
12ns
3
36nC
36nC
7
Share Link: 