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IXTA200N055T2

DC to DC Synchronous Converter Design

IXYS CORPORATION 

DC to DC Synchronous Converter Design

Abdus Sattar, IXYS Corporation

IXAN0068

Overview of Synchronous Converter Power Loss: [1]

The losses in the synchronous converter’s power switches can be defined by:

PTotal = PC + PSW + PGate + PBD

(8)

Where PC is the conduction loss, Psw is the switching power loss, PGate is the gate drive

loss and PBD is the body diode loss. In addition, inductor equivalent DC resistance losses

and output capacitor’s ESR loss play significant role in the converter design.

MOSFET Q1 and Q2’s Power Loss: [1]

The conduction losses: (replace D to 1-D for Sync FET, Q2):

PC = (I O D) 2 • RDS (on)

(9)

The gate-charge losses:

Pg−C = VGS • Qg • f s

(10)

The switching losses:

Figure 5: Transitions waveforms of MOSFET for inductive load

The switching loss is,

PSwitching = Pt (on) + Pt (off )

= [VDS (max){I DS (on) • tt (on) + I DS (off ) • tt(off ) } • f s ]

2

(11)

MOSFET Body Diode Loss: [1]

The body diode loss is a function of dead time and in every switching cycle; there are two

dead-time intervals, td1 and td2. The dead-time is defined as the time required when both

the MOSFETs Q1 and Q2 are OFF in order to prevent shoot-through.

5

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