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IXDP610 Datasheet PDF : 8 Pages
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IXDP 610
IXDP610's Control latch. The "%"
columns express the dead-time as a
percent of the PWM cycle time.
If a zero is written to the 7/8 bit the
IXDP610 is programmed for 7-bit
resolution, writing a one programs the
IXDP610 for 8-bit resolution. If a one is
written to the Divide bit, the external
clock (CLK) is divided by two before
being presented to the Pulse Width
counter; a zero in the Divide bit passes
CLK directly to the Pulse Width
Counter with no division of the
frequency. For a given CLK frequency
one can select three different PWM
frequencies: CLK/128, CLK/256, and
CLK/512. (CLK/256 can be selected for
either 7-bit or 8-bit resolution.
Software Considerations
Initialization and the Lock Bit
After power-up, the IXDP610 should
be reset via the RST input. Doing so
will guarantee the initial state of the
DPWM and effectively write a
01000111 binary to the Control latch.
Thus, after asserting RST, the
IXDP610 is set to the following state:
G Stop is asserted, disabling OUT1
and OUT2
G 8-bit resolution is selected
G CLK is divided by one (not divided
by two)
G Lock bit is “UNLOCKED”
G Dead-time Counter is set for
maximum dead-time.
Asserting RST is the only means by
which the Lock bit can be “unlocked".
The lock bit must be cleared in order
to write to all other bits in the Control
latch, except the Stop bit.
The IXDP610 does not undergo an
internal reset on power-up; therefore,
it is recommended that the system
reset be connected to the DPWM, as
in Fig. 5. If one wishes to allow soft-
ware control over the RST input, they
should “OR” the system reset and an
I/O bit together, so the DPWM has a
known state following system reset.
Before initializing the Control latch,
one should first write a valid number
to the Pulse Width latch (i.e., a num-
ber that results in 0 V applied to the
load). Asserting RST clears the Pulse
Width latch.
7
During a write to the Control latch, all
bits can be modified simultaneously,
including the Lock bit. Thus, only one
write is necessary to set the dead-
time: 1) assert the Lock bit; 2) choose
the Divide bit state; 3) choose the
resolution. In most applications it is
not necessary to change the dead-
time bit, the Divide bit, or the 7/8 bit
“on the fly”. Therefore, it is recom-
mended that the Lock bit be asserted
during initialization of the Control
latch. Setting the Lock bit guarantees
that a software runaway will not
modify the state of the dead-time bit,
thereby preventing an accidental
short of the bridge. If the RST input is
accessible to the software (via an I/O
bit, spare chip select, etc.), the
hardware associated with asserting
the RST input should be designed to
minimize the possibility of resetting
the IXDP610 in the event of a soft-
ware runaway, since asserting the
RST input clears the Lock bit, allo-
wing modification of the DPWM's
Control latch.
Software Overflow Protection
In many applications, the Pulse
Width number written by the micro-
processor to the IXDP610’s Pulse
Width latch is the result of closed-
loop numeric calculations. Depending
on the algorithm used, the calculated
PWM number may be susceptible to
overflow, i.e. the calculated PWM
number could be larger than the
available 8-bits (or 7-bits) provided in
the Pulse Width latch. If this is the
case, it is important that the software
checks for overflow conditions before
writing a number to the Pulse Width
latch. Following is an example
assuming 8-bit resolution:
if (PWM__num < 0), check for
underflow, PWM__num = 0, set to
minimum limit
else if (PWM__num > 255), check for
overflow, PWM__num = 255; set to
maximum limit
Effect of Dead-time on Duty Cycle
The IXDP610 has been designed to
generate PWM signals that range
from 0 % to 100 %, inclusive. When
zero dead-time has been selected
(by writing 000 to the dead-time bits)
the duty cycle of a PWM cycle can be
determined by using the formulae
shown on page 32/33. Fig. 6 illustra-
tes the effect that a nonzero dead-
time has on the PWM waveform.
The dead-time feature built into the
IXDP610 guarantees that both OUT1
and OUT2 remain off for the duration
of the dead-time period. A dead-time
period occurs each time either OUT1
or OUT2 turns off; the dead-time
period overlaps the on-time of an
output (see Fig. 6c). Thus, if the
desired duty cycle is such that the
PWM
Fre-
quency
kHz
Min.
% µs
Dead-time Options
Step
%
µs
Max.
%
µs
300
0 0 1.56 0.052 10.9
0.363
200
0 0 1.56 0.078 10.9
0.547
100
0 0 0.78 0.078 5.5
0.547
100
0 0 1.56 0.156 10.9
1.094
50
0 0 0.39 0.078 2.7
0.547
50
0 0 0.78 0.156 5.5
1.094
50
0 0 0.78 0.156 5.5
1.094
50
0 0 1.56 0.312 10.9
2.188
20
0 0 0.39 0.195 2.7
1.367
20
0 0 0.78 0.391 5.5
2.734
20
0 0 0.78 0.391 5.5
2.734
20
0 0 1.56 0.781 10.9
5.469
5
0 0 0.39 0.781 2.7
5.469
5
0 0 0.78 1.562 5.5 10.94
5
0 0 0.78 1.562 5.5 10.94
5
0 0 1.56 3.125 10.9 21.88
Table 4. Sample PWM Frequency and Dead-time Options
CLK
MHz
38.4
25.6
25.6
12.8
25.6
12.8
12.8
6.4
10.24
5.12
5.12
2.56
2.56
1.28
1.28
0.64
7/8 DIV
bit bit
00
00
10
00
11
10
01
00
11
10
01
00
11
10
01
00
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