IXDP610 Ver la hoja de datos (PDF) - IXYS CORPORATION

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IXDP610

Bus Compatible Digital PWM Controller

IXYS CORPORATION 

Pin Description IXDP 610PI

D0

D1

D2

D3

D4

D5

D6

D7

GND

IXYS

IXDP610PI

Sym. Pin Description

CS

WR

RST

SEL

ODIS

CLK

VCC

OUT1

OUT2

D0 1 DATA BUS - the data bus on

D1 2 the IXDP610 is configured for

D2 3 input only. Data to be written to

D3 4 the IXDP610 is placed on data

D4 5 lines D0 through D7 during a

D5 6 microprocessor write cycle.

D6 7 Data is accepted by the

D7 8 IXDP610 when CHIP SELECT

is low and the WRITE input

goes from a low to a high

state. The SELECT input

determines whether the data

written to the IXDP610 will go

to the Control latch or to the

Pulse Width latch. D0 is the

least significant bit and D7 is

the most significant bit.

GND 9 CIRCUIT GROUND

OUT2 10

OUT1 11

COMPLEMENTARY OUTPUTS

these two outputs provide the

complementary PWM signals.

The base period or cycle time

of these outputs is determined

by the CLOCK and the control

latch.

VCC 12 POWER SUPPLY (5 V ± 10 %)

CLK 13 CLOCK - the frequency of this

input determines the PWM

base frequency. CLK also

drives the internal state

machines. It has no effect on

any data bus transactions.

ODIS 14 OUTPUT DISABLE - asserting

this Schmitt trigger input forces

the complementary outputs to

be immediately disabled

(OUT1 and OUT2 are forced

low). The complementary

outputs will remain low as long

as long as this input is asser-

ted, and for the duration of the

PWM cycle in which OUTPUT

DISABLE goes from low to

high; i.e., the complementary

outputs are not re-enabled

until the beginning of the next

PWM cycle, and then only if

OUTPUT DISABLE and the

Stop bit in the Control latch are

not asserted.

3

IXDP 610

Nomenclature of

Digital PWM Controller

SEL 15 SELECT-this input determines

whether data written into the

IXDP610 goes to the internal

Pulse Width (PW) latch or to

the Control latch. A zero on

this input (low voltage) directs

data to the PW latch; a one on

this input (high voltage) directs

data to the Control latch.

RST 16 RESET-this asynchronous,

active low input disables the

outputs, chooses 8-bit count

mode in the PWM counter,

sets the clock to be "divided

by 1", clears Lock bit, and sets

the dead-time counter to 7.

Asserting RESET writes a

01000111 binary to the Control

latch. Asserting RESET is the

only way in which the Lock bit

in the control latch can be

cleared. Writes to the control

latch that occur after the lock

bit has been set to a one, can

only modify the Stop bit. Any

writes to the control latch,

while the RESET input is

asserted, are ignored. RESET

also clears the PW latch.

WR 17 WRITE-a low-to-high transition

on this input, when CHIP

SELECT is low, causes data to

be written to the selected

IXDP610 latch. If SELECT is

low, the data is written to the

pulse width latch. If SELECT is

high, the data is written to the

control latch.

CS 18 CHIP SELECT - this active low

input enables the WRITE input

so that data may be written

into the IXDP610 latch

selected by the SELECT input.

IXDP 610 P I

IX

DP 610

P

I

(Example)

IXYS

Digital PWM Controller

Package Type

18-Pin Plastic DIP

Temperature Range

Industrial

(-40 to 85°C)

© 2001 IXYS/DEI All rights reserved

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