ISPLSI1016EA Ver la hoja de datos (PDF) - Lattice Semiconductor
Número de pieza
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Fabricante
ISPLSI1016EA Datasheet PDF : 13 Pages
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Specifications ispLSI 1016EA
Internal Timing Parameters1
PARAM. #
DESCRIPTION
-200
-125
-100
UNITS
MIN. MAX. MIN. MAX. MIN. MAX.
Outputs
tob
49 Output Buffer Delay
— 0.9 — 1.7 — 2.0 ns
tsl
50 Output Buffer Delay, Slew Limited Adder
— 5.0 — 5.0 — 5.0 ns
toen
51 I/O Cell OE to Output Enabled
— 3.1 — 4.0 — 5.1 ns
todis
52 I/O Cell OE to Output Disabled
— 3.1 — 4.0 — 5.1 ns
tgoe
53 Global OE
— 1.4 — 3.0 — 3.9 ns
Clocks
tgy0
tgy1
tgcp
54 Clock Delay, Y0 to Global GLB Clock Line (Ref. clk)
55 Clock Delay, Y1 to Global GLB Clock Line
56 Clock Delay, Clock GLB to Global GLB Clock Line
0.9
0.9
0.8
0.9
0.9
1.8
W 1.1 1.1 1.9
E0.9 0.9 1.5
N0.8 1.8 0.8
1.9
1.5
1.8
ns
ns
ns
tioy1
57 Clock Delay, Y1 to I/O Cell Global Clock Line
R tiocp
58 Clock Delay, Clock GLB to I/O Cell Global Clock Line
O Global Reset
F tgr
59 Global Reset to GLB and I/O Registers
ispMA5CVHD4EAS5IGNS 1. Internal Timing Parameters are not tested and are for reference only.
0.0 0.0
0.8 2.8
— 0.0
0.0
0.8
—
0.0
2.8
2.1
0.0 0.0 ns
0.8 2.8 ns
— 5.1 ns
Table 2-0037A/1016EA
v.2.6
USE
8
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