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SC2000

Universal Timeslot Interchange

Philips Electronics 

Philips Semiconductors

Universal Timeslot Interchange

Preliminary specification

SC2000

OVERVIEW

The SC2000 is a custom VLSI circuit

optimized for use in the call processing

environment. The SC2000 provides a

cost-effective means of implementing

the interface between a high speed

internal TDM bus and an external

(expansion) TDM bus. Internal buffer-

ing allows the exchange of data between

TDM buses of different speeds and

architectures.

The SC2000 supports two external bus

formats; SCbus/ST-BUS and PEB,

and two internal bus formats; SCbus/

ST-BUS and PEB. It is compatible with

SCSA, PEB, or MVIP requirements.

SCbus operation is also compatible

with the Siemens PCM Highway.

The switching function and operational

configurations of the SC2000 are fully

software programmable. The processor

bus interface is pin configured, allowing

ease of use with a wide variety of indus-

try-standard CPUs.

DESCRIPTION

The primary function of the SC2000 is

to exchange digital data between the

time slot on the local bus and the time

slot on the expansion bus . A micropro-

cessor interface allows the host CPU to

define the time slots and serial streams

between which the data is exchanged.

SCbus/ST-BUS Mode

In SCbus mode the serial streams of the

external bus can be programmed to

operate at 2.048 Mbps, 4.096 Mbps or

8.192 Mbps. The local bus will always

operate at 2.048 Mbps.

The local-to-external bus switch con-

nection is defined by the contents of the

destination routing memory. There are

32 destination routing memory loca-

tions, one corresponding to each time

slot of the local bus. The data stored in

the destination routing memory selects

the time slot and serial stream of the ex-

pansion bus to which the local bus input

(SI) will be connected.

The external-to-local bus switch con-

nection is defined by the contents of the

source routing memory. There are 32

source routing memory locations, one

corresponding to each time slot of the

local bus. The data stored in the source

routing memory selects the time slot and

serial stream to which the local bus out-

put (SO) will be connected.

Writing data into the routing memories

is synchronized with the SCbus timing

so that routing data is only changed on

frame boundaries.

All serial data is buffered in holding reg-

isters. The entire contents of the holding

register are transferred to the output

registers on frame boundaries. This

architecture introduces a constant

one-frame delay through the switch.

This constant delay allows bundled

time slots to be switched.

PEB Mode

In PEB mode the serial streams of the

external bus and the local bus may be

selected to run at either 1.544 Mbps

or 2.048 Mbps.

When PEB mode is selected, one of four

PEB configurations may be used:

1. PEB resource mode, without

switching.

2. PEB network mode, without

switching.

3. PEB resource mode, with switching.

4. PEB network mode, with switching.

When switching is not selected the serial

data is simply buffered between the local

bus and the PEB. This maintains the

data position relative to the multi-frame

sync and allows robbed-bit or CAS

signals to propagate transparently.

When switching is selected the serial

data is transferred between the local and

PEB buses via the switching matrix. The

one-frame delay that occurs requires

that robbed-bit or CAS signals be

handled specially.

The advantages of modes with

switching are:

• Timing delays between the local and

PEB bus are decoupled by the switch

matrix

• The local bus can access all PEB data

lines (SERR, SERT, and L_SERT)

• SO can be set to high impedance

on frame boundaries, allowing a

bi-directional local bus to be

implemented

Non-switching modes are the only con-

figurations that support an interface

to an asynchronous PEB.

CPU Data Switching

In addition to switching local bus serial

data to and from the external bus, the

SC2000 also allows the CPU to write

data directly to the external bus. The

chip provides a frame-sync generated

interrupt which enables a group of

time slots to be accessed from the

same frame.

Internal Bus Data Switching

The Source Routing Memory Local

Connect Enable selects the switching

of data from any SI time slot to any SO

time slot. This operation introduces a

constant two-frame delay, as the data

passes through the switch twice.

Loopback Mode

The SCbus Loopback Mode electrically

isolates the SC2000 from the external

bus but still allows access to the local

bus. This mode is intended for isolating

the board from the external bus while

diagnostic tests are being run. A

CLK_IN source is required for this

mode. The recommended CLK_IN

frequencies are 2.048 MHz, 4.096

MHz, 8.192 MHz, 16.384 MHz, or

32.768 MHz.

2000 Sep 07

4

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