ISL90840UAV2027Z Ver la hoja de datos (PDF) - Intersil
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ISL90840UAV2027Z Datasheet PDF : 13 Pages
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ISL90840
Analog Specifications Over recommended operating conditions unless otherwise stated. (Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
TYP
MIN (NOTE 4)
TCR
Resistance temperature coefficient DCP register set between 20 hex and FF hex
±45
(Note 17)
MAX
UNIT
ppm/°C
Operating Specifications Over the recommended operating conditions unless otherwise specified.
SYMBOL
ICC1
ISB
PARAMETER
VCC supply current (volatile
write/read)
VCC current (standby)
TEST CONDITIONS
TYP
MIN (NOTE 4) MAX
fSCL = 400kHz; SDA = Open; (for I2C, active,
1
read and write states)
VCC = +5.5V, I2C Interface in Standby State,
Temperature range from -40°C to 85°C
2
5
VCC = +5.5V, I2C Interface in Standby State,
Temperature range from -40°C to 105°C
2
8
VCC = +3.6V, I2C Interface in Standby State,
Temperature range from -40°C to 85°C
0.8
2
VCC = +3.6V, I2C Interface in Standby State,
Temperature range from -40°C to 105°C
0.8
5
ILkgDig Leakage current, at pins A0, A1, A2, Voltage at pin from GND to VCC
-10
10
SDA, and SCL
tDCP
DCP wiper response time
SCL falling edge of last bit of DCP data byte
1
(Note 18)
to wiper change
SERIAL INTERFACE SPECS
VIL
A2, A1, A0, SDA, and SCL input buffer
LOW voltage
-0.3
0.3*VCC
VIH
A2, A1, A0, SDA, and SCL input buffer
HIGH voltage
Hysteresis SDA and SCL input buffer hysteresis
(Note 18)
VOL
SDA output buffer LOW voltage,
(Note 18) sinking 4mA
0.7*VCC
0.05*
VCC
0
VCC+0.3
0.4
Cpin A2, A1, A0, SDA, and SCL pin
10
(Note 18) capacitance
fSCL
SCL frequency
400
tIN
Pulse width suppression time at SDA Any pulse narrower than the max spec is
50
(Note 18) and SCL inputs
suppressed
tAA
SCL falling edge to SDA output data SCL falling edge crossing 30% of VCC, until
900
(Note 18) valid
SDA exits the 30% to 70% of VCC window
tBUF
(Note 18)
Time the bus must be free before the SDA crossing 70% of VCC during a STOP
start of a new transmission
condition, to SDA crossing 70% of VCC
during the following START condition
1300
tLOW
tHIGH
tSU:STA
Clock LOW time
Clock HIGH time
START condition setup time
tHD:STA START condition hold time
tSU:DAT Input data setup time
tHD:DAT Input data hold time
Measured at the 30% of VCC crossing
Measured at the 70% of VCC crossing
SCL rising edge to SDA falling edge; both
crossing 70% of VCC
From SDA falling edge crossing 30% of VCC
to SCL falling edge crossing 70% of VCC
From SDA exiting the 30% to 70% of VCC
window, to SCL rising edge crossing 30% of
VCC
From SCL rising edge crossing 70% of VCC
to SDA entering the 30% to 70% of VCC
window
1300
600
600
600
100
0
UNIT
mA
µA
µA
µA
µA
µA
µs
V
V
V
V
pF
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
5
FN8086.2
November 14, 2006
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