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NX25F080A-5TI-R Datasheet PDF : 25 Pages
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NX25F080A
Pin Descriptions
Package
The NX25F080A is available in a 24/28-pin TSOP (Type II)
surface mount package. See Figure 3 and Table 1 for pin
assignments. All interface and supply pins are on one side
of the package. The “No Connect” (NC) pins are not
connected to the device, allowing the pads and the area
around them to be used for routing PCB system traces. The
50 mil pin-to-pin spacing of the package eases assembly
and pre-programming compared to other Flash devices
that use 25 mil spacing. The NX25F080A is also available
in a cost-effective and space-efficient removable Serial
Flash Module package (see NX25Mxxx data sheet).
Serial Data Input (SI)
The SPI bus Serial Data Input (SI) provides a means for
data to be written to (shifted into) the device.
Serial Data Output (SO)
The SPI bus Serial Data Output (SO) provides a means for
data to be read from (shifted out of) the device during a read
operation. When the device is deselected (CS=1 or
HOLD=0) the SO pin is in a high-impedance state.
Serial Clock (SCK)
All commands and data written to the Serial Input (SI) are
clocked relative to the rising edge of the Serial Clock (SCK).
By default all data read from the Serial Data Output (SO) is
clocked relative to the falling edge of SCK, allowing com-
patibility with standard SPI systems. The user may specify
HOLD R/B 1
SCK 2
SO 3
Vcc 4
NC 5
NC 6
28 NC
27 NC
26 NC
25 NC
24 NC
23 NC
NC 9
NC 10
CS 11
WP 12
SI 13
GND 14
20 NC
19
NC
18
NC
17
NC
16
NC
15
NC
Figure 3. NX25F080A Pin Assignments
1 reading relative to the rising edge of SCK by changing the
setting of the RCE bit in the Configuration Register (see
Figure 6). Clock rates of up to 16 MHz for 5V devices and
up to 8 MHz for 3V devices are supported.
Chip Select (CS)
2
The NX25F080A is selected for operation when the Chip
Select Input (CS) is asserted low. Upon power-up, an initial
low to high transition of CS is required before any com-
3 mand sequence will be acknowledged. The device can be
de-selected to a non-active state when CS is brought high.
Once deselected, the SO pin will enter a high-impedance
state and power consumption will decrease to standby
levels unless programming is in process, in which case
standby will resume when programming is complete.
4
Write Protect (WP)
The Write Protect Input (WP) works in conjunction with the
5 write protect range set in the Configuration Register bits.
When WP is asserted (active LOW) the entire Flash
memory array is write protected. When HIGH, any Flash
memory sector can be written to unless its address is within
the write protect range that is set in the Configuration
Register.
6
Hold or Ready/Busy (HOLD or R/B)
This multi-function pin can serve either as a Hold Input
7 (HOLD) or as a Ready-Busy Output (R/B). The pin function
is user-programmable via the non-volatile Configuration
Register. Factory-programmed as a no connect, the pin can
be reconfigured as a Ready/Busy output or as a Hold input
by setting the Configuration Register. See the Configuration
8 Register section of this data sheet for further details.
Warning: this pin is tied low in the Serial Flash Module and
must be left as a no connect (NC).
9 Power Supply Pins (Vcc and Gnd)
The NX25F080A support single power supply read and
erase/write operations in 5V and 3V Vcc versions. Typical
active power is as low as 5 mA for 3V versions with standby
current in the 1 µA range.
10
Table 1. Pin Descriptions
SI
SO
SCK
CS
WP
Hold, R/B
Vcc
Serial Data Input
11
Serial Data Output
Serial Clock Input
Chip Select Input
Write Protect Input
12
Hold Input or Read Busy Output
Power Supply
NexFlash Technologies, Inc.
3
PRELIMINARY NXSF005C-0699
06/11/99 ©
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