ISL1209 Ver la hoja de datos (PDF) - Intersil

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componentes Descripción

Fabricante

ISL1209

Low Power RTC with Battery Backed SRAM and Event Detection

Intersil 

ISL1209

SDA vs. SCL Timing

tF

tHIGH

SCL

tSU:STA

SDA

(INPUT TIMING)

tSU:DAT

tHD:STA

SDA

(OUTPUT TIMING)

tLOW

tR

tHD:DAT

tAA

tDH

Symbol Table

WAVEFORM INPUTS

Must be steady

OUTPUTS

Will be steady

May change

from LOW

to HIGH

May change

from HIGH

to LOW

Don’t Care:

Changes Allowed

Will change

from LOW

to HIGH

Will change

from HIGH

to LOW

Changing:

State Not Known

N/A

Center Line is

High Impedance

tSU:STO

tBUF

5

FN6109.1

September 27, 2005

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