ISL12023IVZ Ver la hoja de datos (PDF) - Intersil

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ISL12023IVZ

Low Power RTC with Battery-Backed SRAM and Embedded Temp Compensation ±5ppm with Auto Daylight Saving

Intersil 

ISL12023

SDA vs SCL Timing

tF

tHIGH

tLOW

tR

SCL

tSU:STA

SDA

(INPUT TIMING)

SDA

(OUTPUT TIMING)

tSU:DAT

tHD:STA

tHD:DAT

tAA

tDH

EQUIVALENT AC OUTPUT LOAD CIRCUIT FOR VDD = 5V

5.0V

SDA,

IRQ AND FOUT

1533Ω

FOR VOL= 0.4V

AND IOL = 3mA

100pF

FIGURE 1. STANDARD OUTPUT LOAD FOR TESTING THE

DEVICE WITH VDD = 5.0V

Symbol Table

WAVEFORM INPUTS

OUTPUTS

Must be steady

Will be steady

May change

from LOW

to HIGH

May change

from HIGH

to LOW

Don’t Care:

Changes Allowed

Will change

from LOW

to HIGH

Will change

from HIGH

to LOW

Changing:

State Not Known

N/A

Center Line is

High Impedance

tSU:STO

tBUF

6

FN6682.2

June 24, 2009

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