IS61C64B-10J(2002) Ver la hoja de datos (PDF) - Integrated Silicon Solution
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IS61C64B-10J Datasheet PDF : 9 Pages
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IS61C64B
ISSI ®
WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range)
Symbol Parameter
–10 ns
-12 ns
-15 ns
Min. Max.
Min. Max.
Min. Max.
Unit
1
tWC Write Cycle Time
10 —
12 —
15 —
ns
tSCE CE to Write End
9—
10 —
12 —
ns
tAW Address Setup Time to Write End
9—
10 —
12 —
ns
2
tHA Address Hold from Write End
0—
0—
0—
ns
tSA Address Setup Time
tPWE(4) WE Pulse Width
0—
0—
0—
ns
8—
8—
10 —
ns
3
tSD Data Setup to Write End
8—
8—
9—
ns
tHD Data Hold from Write End
0—
0—
0—
ns
tHZWE(2) WE LOW to High-Z Output
—6
—6
—7
ns
4
tLZWE(2) WE HIGH to Low-Z Output
0—
0—
0—
ns
5 Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and
output loading specified in Figure 1a.
2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write,
6 but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling
edge of the signal that terminates the write.
7
8
9
10
11
12
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. D
07/01/02
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