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5 MHz–400 MHz 100 dB High Precision Limiting-Logarithmic Amplifier

Analog Devices 

AD8306

the intercept to –108 dBV, by raising the RSSI output voltage for

zero input, and to provide temperature compensation, resulting

in a stable intercept. For zero signal conditions, all the detector

output currents are equal. For a finite input, of either polarity,

their difference is converted by the output interface to a single-

sided voltage nominally scaled 20 mV/dB (400 mV per decade), at

the output VLOG (Pin 16). This scaling is controlled by a sepa-

rate feedback stage, having a tightly controlled transcon-

ductance. A small uncertainty in the log slope and intercept

remains (see Specifications); the intercept may be adjusted (see

Applications).

SUMMED 1.3k⍀

DETECTOR

OUTPUTS

LGP

CURRENT

1.3k⍀ MIRROR

ISOURCE

>50mA

ON DEMAND

C1

3.5pF

VPS2

FLTR

CF

LGN

IT

3.3k⍀

VLOG

250␮s

TRANSCONDUCTANCE

DETERMINES SLOPE

3.3k⍀

125␮A

ISINK

FIXED

1mA

VLOG

20mV/dB

COMM

Figure 23. Simplified RSSI Output Interface

The RSSI output bandwidth, fLP, is nominally 3.5 MHz. This is

controlled by the compensation capacitor C1, which may be

increased by adding an external capacitor, CF, between FLTR

(Pin 10) and VLOG (Pin 16). An external 33 pF will reduce fLP

to 350 kHz, while 360 pF will set it to 35 kHz, in each case with

an essentially one-pole response. In general, the relationships

(for fLP in MHz) are:

CF

= 12.7×10–10

fLP

– 3.5

pF ;

fLP

=

12.7 ×10−6

CF + 3.5 pF

(1)

Using a load resistance of 50 Ω or greater, and at any tempera-

ture, the peak output voltage may be at least 2.4 V when using a

supply of 4.5 V, and at least 2.1 V for a 3 V supply, which is

consistent with the maximum permissible input levels. The incre-

mental output resistance is approximately 0.3 Ω at low frequen-

cies, rising to 1 Ω at 150 kHz and 18 Ω at very high frequencies.

The output is unconditionally stable with load capacitance, but

it should be noted that while the peak sourcing current is

over 100 mA, and able to rapidly charge even large capacitances,

the internally provided sinking current is only 1 mA. Thus, the

fall time from the 2 V level will be as long as 2 µs for a 1 nF

load. This may be reduced by adding a grounded load resistance.

USING THE AD8306

The AD8306 exhibits very high gain from 1 MHz to over 1 GHz,

at which frequency the gain of the main path is still over 65 dB.

Consequently, it is susceptible to all signals, within this very

broad frequency range, that find their way to the input termi-

nals. It is important to remember that these are quite indistin-

guishable from the “wanted” signal, and will have the effect of

raising the apparent noise floor (that is, lowering the useful

dynamic range). Therefore, while the signal of interest may be

an IF of, say, 200 MHz, any of the following could easily be

larger than this signal at the lower extremities of its dynamic

range: a 60 Hz hum, picked up due to poor grounding tech-

niques; spurious coupling from digital logic on the same PC

board; a strong EMI source; etc.

Very careful shielding is essential to guard against such un-

wanted signals, and also to minimize the likelihood of instability

due to HF feedback from the limiter outputs to the input. With

this in mind, the minimum possible limiter gain should be used.

Where only the logarithmic amplifier (RSSI) function is re-

quired, the limiter should be disabled by omitting RLIM and

tying the outputs LMHI and LMLO directly to VPS2. A good

ground plane should be used to provide a low impedance con-

nection to the common pins, for the decoupling capacitor(s)

used at VPS1 and VPS2, and at the output ground. Note that

COM2 is a special ground pin serving just the RSSI output.

The four pins labeled PADL tie down directly to the metallic

lead frame, and are thus connected to the back of the chip. The

process on which the AD8306 is fabricated uses a bonded-wafer

technique to provide a silicon-on-insulator isolation, and there is

no junction or other dc path from the back side to the circuitry

on the surface. These paddle pins must be connected directly to

the ground plane using the shortest possible lead lengths to

minimize inductance.

The voltages at the two supply pins should not be allowed to

differ greatly; up to 500 mV is permissible. It is desirable to

allow VPS1 to be slightly more negative than VPS2. When the

primary supply is greater than 2.7 V, the decoupling resistors R1

and R2 (Figure 24) may be increased to improve the isolation

and lower the dissipation in the IC. However, since VPS2 sup-

ports the RSSI load current, which may be large, the value of

R2 should take this into account.

Basic Connections for Log (RSSI) Output

Figure 24 shows the connections required for most applications.

The AD8306 is enabled by connecting ENBL to VPS1. The

device is put into the sleep mode by grounding this pin. The

inputs are ac-coupled by C1 and C2, which normally should

have the same value (CC). The input is, in this case, terminated

with a 52.3 Ω resistor that combines with the AD8306’s input

resistance of 1000 Ω to give a broadband input impedance of

50 Ω. Alternatively an input matching network can be used (see

Input Matching section).

R1

10⍀

0.1␮F

1 COM2

2 VPS1

VLOG 16

VPS2 15

R2

10⍀

0.1␮F

C1

0.01␮F

SIGNAL

INPUTS

C2

0.01␮F

RT

52.3⍀

3 PADL

PADL 14

AD8306

4 INHI

LMHI 13

5 INLO

LMLO 12

6 PADL

PADL 11

7 COM1

FLTR 10

ENABLE

8 ENBL

LMDR 9

VS (2.7V TO 6.5V)

RSSI

CF

(OPTIONAL

SEE TEXT)

Figure 24. Basic Connections for RSSI (Log) Output

The 0.01 µF coupling capacitors and the resulting 50 Ω input

impedance give a high-pass corner frequency of around 600 kHz.

(1/(2 π RC)), where C = (C1)/2. In high frequency applications,

this corner frequency should be placed as high as possible, to

minimize the coupling of unwanted low frequency signals. In

REV. A

–9–

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