5962-9864601QEA Ver la hoja de datos (PDF) - Analog Devices

Número de pieza

componentes Descripción

Fabricante

5962-9864601QEA

5 MHz–400 MHz 100 dB High Precision Limiting-Logarithmic Amplifier

Analog Devices 

AD8306

voltage sensitivity. Most interfaces have additional small junc-

tion capacitances associated with them, due to active devices or

ESD protection; these may be neither accurate nor stable.

Component numbering in each of these interface diagrams is

local.

Enable Interface

The chip-enable interface is shown in Figure 20. The current in

R1 controls the turn-on and turn-off states of the band-gap

reference and the bias generator, and is a maximum of 100 µA

when Pin 8 is taken to 5 V. Left unconnected, or at any voltage

below 1 V, the AD8306 will be disabled, when it consumes a

sleep current of much less than 1 µA (leakage currents only); when

tied to the supply, or any voltage above 2 V, it will be fully enabled.

The internal bias circuitry requires approximately 300 ns for

either OFF or ON, while a delay of some 6 µs is required for the

supply current to fall below 10 µA.

ENBL

R1

60k⍀

1.3k⍀

TO BIAS

ENABLE

COMM

50k⍀ 4k⍀

Figure 20. Enable Interface

Input Interface

Figure 21 shows the essentials of the signal input interface. The

parasitic capacitances to ground are labeled CP; the differential

input capacitance, CD, mainly due to the diffusion capacitance

of Q1 and Q2. In most applications both input pins are ac-

coupled. The switch S closes when Enable is asserted. When

disabled, the inputs float, bias current IE is shut off, and the

coupling capacitors remain charged. If the log amp is disabled

for long periods, small leakage currents will discharge these

capacitors. If they are poorly matched, charging currents at

power-up can generate a transient input voltage which may

block the lower reaches of the dynamic range until it has be-

come much less than the signal.

handled using a supply of 4.5 V or greater. When using a fully-

balanced drive, the +3 dBV level may be achieved for the sup-

plies down to 2.7 V and +9 dBV using >4.5 V. For frequencies

in the range 10 MHz to 200 MHz these high drive levels are

easily achieved using a matching network. Using such a net-

work, having an inductor at the input, the input transient is

eliminated.

Limiter Output Interface

The simplified limiter output stage is shown in Figure 22. The

bias for this stage is provided by a temperature-stable reference

voltage of nominally 400 mV which is forced across the exter-

nal resistor RLIM connected from Pin 9 (LMDR, or limiter

drive) by a special op amp buffer stage. The biasing scheme

also introduces a slight “lift” to this voltage to compensate for

the finite current gain of the current source Q3 and the output

transistors Q1 and Q2. A maximum current of 10 mA is per-

missible (RLIM = 40 Ω). In special applications, it may be desir-

able to modulate the bias current; an example of this is provided

in the Applications section. Note that while the bias currents are

temperature stable, the ac gain of this stage will vary with tem-

perature, by –6 dB over a 120°C range.

A pair of supply and temperature stable complementary cur-

rents is generated at the differential output LMHI and LMLO

(Pins 12 and 13), having a square wave form with rise and fall

times of typically 0.6 ns, when load resistors of 50 Ω are used.

The voltage at these output pins may swing to 1.2 V below the

supply voltage applied to VPS2 (Pin 15).

Because of the very high gain bandwidth product of this ampli-

fier considerable care must be exercised in using the limiter

outputs. The minimum necessary bias current and voltage

swings should be used. These outputs are best utilized in a

fully-differential mode. A flux-coupled transformer, a balun, or

an output matching network can be selected to transform these

voltages to a single-sided form. Equal load resistors are recom-

mended, even when only one output pin is used, and these

should always be returned to the same well decoupled node on

the PC board. When the AD8306 is used only to generate an

RSSI output, the limiter should be completely disabled by

omitting RLIM and strapping LMHI and LMLO to VPS2.

VPS2

LMHI LMLO

VPS1

CC INHI

SIGNAL

INPUT

CC INLO

COMM

1.78V

S

3.65k⍀

1.725V

RIN = 1k⍀

1.725V

CP

3.65k⍀

IB = 15mA

67⍀

Q1

CD

2.5pF

20e

RIN = 3k⍀

TO STAGES

1 THRU 5

67⍀

TO 2ND

STAGE

Q2

20e

2.6k⍀

(TOP-END

DETECTORS)

CP 130⍀

GAIN BIAS

1.26V

3.4mA

PTAT

1.3k⍀ 1.3k⍀

FROM FINAL

LIMITER STAGE

2.6k⍀ 1.3k⍀

Q1

4e

Q3

1.3k⍀

Q2

4e

400mV

OA ZERO-TC

COM1

RLIM

LMDR

Figure 21. Signal Input Interface

In most applications, the input signal will be single-sided, and

may be applied to either Pin 4 or 5, with the remaining pin ac-

coupled to ground. Under these conditions, the largest input

signal that can be handled is –3 dBV (sine amplitude of 1 V)

when operating from a 3 V supply; a +3 dBV input may be

Figure 22. Limiter Output Interface

RSSI Output Interface

The outputs from the ten detectors are differential currents,

having an average value that is dependent on the signal input

level, plus a fluctuation at twice the input frequency. The cur-

rents are summed at the internal nodes LGP and LGN shown

in Figure 23. A further current IT is added to LGP, to position

–8–

REV. A

Share Link: