IS25LQ040(2012) Ver la hoja de datos (PDF) - Integrated Silicon Solution

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componentes Descripción

Fabricante

IS25LQ040
(Rev.:2012)

4 Mbit Single Operating Voltage Serial Flash Memory With 104 MHz Dual- or 100MHz Quad-Output SPI Bus Interface

Integrated Silicon Solution 

IS25LQ040

PIN DESCRIPTIONS

SYMBOL TYPE

DESCRIPTION

CE#

SCK

SI (IO0)

SO (IO1)

GND

Vcc

WP#

(IO2)

HOLD#

(IO3)

INPUT

INPUT

INPUT/OUTPUT

INPUT/OUTPUT

INPUT/OUTPUT

INPUT/OUTPUT

Chip Enable: CE# low activates the devices internal circuitries for

device operation. CE# high deselects the devices and switches into

standby mode to reduce the power consumption. When a device is not

selected, data will not be accepted via the serial input pin (Sl), and the

serial output pin (SO) will remain in a high impedance state.

Serial Data Clock

Serial Data Input/Output

Serial Data Input/Output

Ground

Device Power Supply

Write Protect/Serial Data Output: A hardware program/erase protection for all or

part of a memory array. When the WP# pin is low, memory array write-protection

depends on the setting of BP3, BP2, BP1 and BP0 bits in the Status Register.

When the WP# is high, the status register are not write-protected.

When the QE bit of is set ‘‘1’’, the /WP pin (Hardware Write Protect) function is

not available since this pin is used for IO2

Hold: Pause serial communication by the master device without resetting

the serial sequence.

When the QE bit of Status Register is set for ‘‘1’’, the function is Serial Data

Input & Output (for 4xI/O read mode)

Integrated Silicon Solution, Inc.- www.issi.com

Rev. A

3

09/13/2012

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