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IS25LD256C

256Kbit Single Operating Voltage Serial Flash Memory With 100 MHz Dual-Output SPI Bus Interface

Integrated Silicon Solution 

IS25LD256C

REGISTERS (CONTINUED)

PROTECTION MODE

The IS25LD256C have two types of write-protection Table 9. Hardware Write Protection on Status

mechanisms: hardware and software. These are used Register

to prevent irrelevant operation in a possibly noisy

environment and protect the data integrity.

SRWD WP#

Status Register

HARDWARE WRITE-PROTECTION

0

Low

1

Low

Writable

Protected

The devices provide two hardware write-protection

features:

0

High

1

High

Writable

Writable

a. When inputting a program, erase or write status

register instruction, the number of clock pulse is

checked to determine whether it is a multiple of eight

before the executing. Any incomplete instruction

command sequence will be ignored.

b. The Write Protection (WP#) pin provides a

hardware write protection method for BP2, BP1, BP0

and SRWD in the Status Register. Refer to the

STATUS REGISTER description.

c. Write inhibit is 2.4V, all write sequence will be

ignored when Vcc drop to 2.4V and lower

SOFTWARE WRITE PROTECTION

The IS25LD256C also provides two software write

protection features:

a. Before the execution of any program, erase or write

status register instruction, the Write Enable Latch

(WEL) bit must be enabled by executing a Write

Enable (WREN) instruction. If the WEL bit is not

enabled first, the program, erase or write register

instruction will be ignored.

b. The Block Protection (BP2, BP1, BP0) bits allow part

or the whole memory area to be write-protected.

Integrated Silicon Solution, Inc.- www.issi.com

9

Rev. A

09/11/2012

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