IS25LD256C Ver la hoja de datos (PDF) - Integrated Silicon Solution

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IS25LD256C

256Kbit Single Operating Voltage Serial Flash Memory With 100 MHz Dual-Output SPI Bus Interface

Integrated Silicon Solution 

IS25LD256C

REGISTERS (CONTINUED)

Table 6. Status Register Bit Definition

Bit

Bit 0

Bit 1

Bit 2

Bit 3

Bit 4

Bits 5 - 6

Bit 7

Name

WIP

WEL

BP0

BP1

BP2

N/A

SRWD

Definition

Write In Progress Bit:

"0" indicates the device is ready

"1" indicates a write cycle is in progress and the device is busy

Write Enable Latch:

"0" indicates the device is not write enabled (default)

"1" indicates the device is write enabled

Block Protection Bit: (See Table 7 and Table 8 for details)

"0" indicates the specific blocks are not write-protected (default)

"1" indicates the specific blocks are write-protected

Reserved: Always "0"s

Status Register Write Disable: (See Table 9 for details)

"0" indicates the Status Register is not write-protected (default)

"1" indicates the Status Register is write-protected

Read-

/Write

R

R/W

R/W

N/A

R/W

Non-Volatile

bit

No

No

Yes

Yes

Table 8. Block Write Protect Bits for IS25LD256C

Status Register Bits

BP2

BP1

BP0

Not used

0

0

Not used

0

1

Not used

1

0

Not used

1

1

Protected Memory Area

256Kbit

None

None

None

All blocks: 000000h - 007FFFh

Integrated Silicon Solution, Inc.- www.issi.com

8

Rev. A

09/11/2012

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