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IS25LD256C

256Kbit Single Operating Voltage Serial Flash Memory With 100 MHz Dual-Output SPI Bus Interface

Integrated Silicon Solution 

REGISTERS (CONTINUED)

STATUS REGISTER

IS25LD256C

Refer to Tables 5 and 6 for Status Register Format and are allowed. The WEL bit is set by a Write Enable

Status Register Bit Definitions.

(WREN) instruction. Each write register, program and

erase instruction must be preceded by a WREN

The BP0, BP1, BP2, and SRWD are non-volatile

instruction. The WEL bit can be reset by a Write

memory cells that can be written by a Write Status

Disable (WRDI) instruction. It will automatically be the

Register (WRSR) instruction. The default value of the reset after the completion of a write instruction.

BP2, BP1, BP0 were set to “0” and SRWD bits was set

to “0” at factory. Once a “0” or “1”is written, it will not be BP2, BP1, BP0 bits: The Block Protection (BP2, BP1,

changed by device power-up or power-down, and can BP0) bits are used to define the portion of the memory

only be altered by the next WRSR instruction. The

area to be protected. Refer to Tables 7, 8 and 9 for the

Status Register can be read by the Read Status

Block Write Protection bit settings. When a defined

Register (RDSR). Refer to Table 10 for Instruction Set. combination of BP2, BP1 and BP0 bits are set, the

corresponding memory area is protected. Any program

The function of Status Register bits are described as or erase operation to that area will be inhibited. Note:

follows:

a Chip Erase (CHIP_ER) instruction is executed

successfully only if all the Block Protection Bits are set

WIP bit: The Write In Progress (WIP) bit is read-only, as “0”s.

and can be used to detect the progress or completion

of a program or erase operation. When the WIP bit is SRWD bit: The Status Register Write Disable (SRWD)

“0”, the device is ready for a write status register,

bit operates in conjunction with the Write Protection

program or erase operation. When the WIP bit is “1”, (WP#) signal to provide a Hardware Protection Mode.

the device is busy.

When the SRWD is set to “0”, the Status Register is

not write-protected. When the SRWD is set to “1” and

WEL bit: The Write Enable Latch (WEL) bit indicates the WP# is pulled low (VIL), the volatile bits of Status

the status of the internal write enable latch. When the Register (SRWD, BP2, BP1, BP0) become read-only,

WEL is “0”, the write enable latch is disabled, and all and a WRSR instruction will be ignored. If the SRWD is

write operations, including write status register, page set to “1” and WP# is pulled high (VIH), the Status

program, sector erase, block and chip erase operations Register can be changed by a WRSR instruction.

are inhibited. When the WEL bit is “1”, write operations

Table 5. Status Register Format

Default (flash bit)

Bit 7

SRWD

0

Bit 6 Bit 5

Reserved

0

Bit 4

BP2

0

Bit 3

BP1

0

Bit 2

BP0

0

Bit 1

WEL

0

Bit 0

WIP

0

Integrated Silicon Solution, Inc.- www.issi.com

7

Rev. A

09/11/2012

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