IS25C128-2PI Ver la hoja de datos (PDF) - Integrated Silicon Solution

Número de pieza

componentes Descripción

Fabricante

IS25C128-2PI

128K-bit/ 256K-bit SPI SERIAL ELECTRICALLY ERASABLE PROM

Integrated Silicon Solution 

IS25C128

IS25C256

SERIAL INTERFACE DESCRIPTION

MASTER: The device that provides a clock signal.

SLAVE: The IS25C128/256 is a slave because the clock

signal is an input.

TRANSMITTER/RECEIVER: The IS25C128/256 has both

data input (SI) and data output (SO).

MSB: The most significant bit. It is always the first bit

transmitted or received.

OP-CODE: The first byte transmitted to the slave follow-

ing CS transition to LOW. If the OP-CODE is a valid

member of the IS25C128/256 instruction set (Table 3),

then it is decoded appropriately. If the OP-CODE is not

valid, and the SO pin remains in high impedance.

BLOCK DIAGRAM

STATUS

REGISTER

SI

CS

WP

SCK

DATA

REGISTER

MODE

DECODE

LOGIC

CLOCK

HOLD

VCC

GND

16K x 8/32K x 8

MEMORY ARRAY

ADDRESS

DECODER

OUTPUT

BUFFER

SO

Integrated Silicon Solution, Inc. — 1-800-379-4774

AdvancedInformation Rev. 00E

06/13/06

ISSI ®

3

Share Link: