MT4LC4M16F5-6 Ver la hoja de datos (PDF) - Micron Technology

Número de pieza

componentes Descripción

Fabricante

MT4LC4M16F5-6

4 MEG x 16 FPM DRAM

Micron Technology 

4 MEG x 16

FPM DRAM

FAST PAGE MODE ACCESS

Each location in the DRAM is uniquely addressable,

as mentioned in the General Description. Use of both

CAS# signals results in a word access via the 16 I/O pins

(DQ0-DQ15). Use of only one of the two results in a

BYTE access cycle. CASL# transitioning LOW selects an

access cycle for the lower byte (DQ0-DQ7), and CASH#

transitioning LOW selects an access cycle for the upper

byte (DQ8-DQ15). General byte and word access timing

is shown in Figures 1 and 2.

Additionally, both bytes must always be of the same

mode of operation if both bytes are active. A CAS#

precharge must be satisfied prior to changing modes of

operation between the upper and lower bytes. For

example, an EARLY WRITE on one byte and a LATE

WRITE on the other byte are not allowed during the

same cycle. However, an EARLY WRITE on one byte and

a LATE WRITE on the other byte, after a CAS# precharge

has been satisfied, are permissible.

The WE# signal must be activated to execute a

WRITE operation; otherwise a READ operation will be

performed. The OE# signal must be activated to enable

the DQ output drivers for a read access and can be

deactivated to disable output data if necessary.

FAST-PAGE-MODE operations are always initiated

with a row address strobed in by the RAS# signal,

followed by a column address strobed in by CAS#, just

like for single location accesses. However, subsequent

column locations within the row may then be accessed

at the page mode cycle time. This is accomplished by

cycling CAS# while holding RAS# LOW and entering

new column addresses with each CAS# cycle. Returning

RAS# HIGH terminates the FAST-PAGE-MODE

operation.

FUNCTIONAL BLOCK DIAGRAM

MT4LC4M16F5 (12 row addresses)

WE#

CASL#

CASH#

CAS#

NO. 2 CLOCK

GENERATOR

COLUMN-

10

ADDRESS

BUFFER(10)

REFRESH

CONTROLLER

A0-

A11

REFRESH

COUNTER

12

ROW-

12

ADDRESS

12

BUFFERS (12)

RAS#

NO. 1 CLOCK

GENERATOR

4 Meg x 16 FPM DRAM

D28_2.p65 – Rev. 5/00

DATA-IN BUFFER

16

DATA-OUT

16

BUFFER

16

16

10

COLUMN

DECODER

1,024

SENSE AMPLIFIERS

I/O GATING

1,024 x 16

4,096

4,096 x 16

4,096 x 1,024 x 16

MEMORY

ARRAY

DQ0-

DQ15

OE#

VDD

VSS

2

Micron Technology, Inc., reserves the right to change products or specifications without notice.

©2000, Micron Technology, Inc.

Share Link: