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NM25C041

4K-Bit Serial Interface CMOS EEPROM (Serial Peripheral Interface (SPI™) Synchronous Bus)

Fairchild Semiconductor 

Functional Description (Continued)

The NM25C041 is capable of a four byte PAGE WRITE operation.

After receipt of each byte of data the two low order address bits are

internally incremented by one. The seven high order bits of the

address will remain constant. If the master should transmit more

than four bytes of data, the address counter will “roll over”, and the

previously loaded data will be reloaded. See Figure 10.

Note that the first four bits are don’t care bits followed by BP1 and

BP0 then two additional don’t care bits. Programming will start

after the CS pin is forced back to a high level. As in the WRITE

instruction the LOW to HIGH transition of the CS pin must occur

during the SCK low time immediately after clocking in the last don’t

care bit. See Figure 12.

FIGURE 10. 4 Page Byte Write

CS

SI

WRITE

OP-CODE

BYTE

ADDR(n)

DATA

(n)

DATA

(n+1)

DATA

(n+2)

DATA

(n+3)

SO

,,,,,,,,,,,,, DS800002-13

At the completion of a WRITE cycle the device is automatically

,,,,,, returned to the write disable state.

FIGURE 12. Start WRSR Condition

CS

tCSN

SCK

SI

tDIS

tDIN

BP0

SO

DS800002-15

The READY/BUSY status of the device can be determined by

If the WP pin is forced low or the device is not WRITE enabled, the executing a READ STATUS REGISTER (RDSR) instruction. Bit 0

device will ignore the WRITE instruction and return to the standby = 1 indicates that the WRSR cycle is still in progress and Bit 0 =

state when CS is forced high. A new CS falling edge is required to 0 indicates that the WRSR cycle has ended.

re-initialize the serial communication.

WRITE STATUS REGISTER (WRSR): The WRITE STATUS

REGISTER (WRSR) instruction is used to program the non-

At the completion of a WRSR cycle the device is automatically

returned to the write disable state.

volatile status register Bits 2 and 3 (BP0 and BP1). As in the

WRITE mode the WRITE PROTECT (WP) pin must be held high

and two separate instructions must be executed. The chip must

first be write enabled via the WRITE ENABLE instruction and then

a WRSR instruction must be executed.

The WRSR command requires the following sequence. The CS

line is pulled low to select the device and then the WRSR op-code

is transmitted on the SI line followed by the data to be programmed

(see Figure 11).

,,,,,,, FIGURE 11. Write Status Register

CS

SI

WRSR

OP-CODE

SR_DATA

XXXXBP1BP0XX

SO

DS800002-14

NM25C041 Rev. D.1

8

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