CY7C0241(1999) Ver la hoja de datos (PDF) - Cypress Semiconductor

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componentes Descripción

Fabricante

CY7C0241
(Rev.:1999)

4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with Sem, Int, Busy

Cypress Semiconductor 

CY7C024/0241

CY7C025/0251

Switching Waveforms

Read Cycle No. 1 (Either Port Address Access)[18, 19, 20]

tRC

ADDRESS

DATA OUT

tAA

tOHA

PREVIOUS DATA VALID

Read Cycle No. 2 (Either Port CE/OE Access)[18, 21, 22]

CE and

LB or UB

OE

DATA OUT

ICC

CURRENT

ISB

tACE

tDOE

tLZOE

tLZCE

tPU

Read Cycle No. 3 (Either Port)[18, 20, 21, 21, 22]

tRC

ADDRESS

tAA

UB or LB

CE

DATA OUT

tLZCE

tABE

tACE

tLZCE

DATA VALID

tOHA

tHZCE

tHZOE

DATA VALID

tPD

tOHA

tHZCE

tHZCE

Notes:

18. R/W is HIGH for read cycles

19. Device is continuously selected CE = VIL and UB or LB = VIL. This waveform cannot be used for semaphore reads.

20. OE = VIL.

21. Address valid prior to or coincident with CE transition LOW.

22. To access RAM, CE = VIL, UB or LB = VIL, SEM = VIH. To access semaphore, CE = VIH, SEM = VIL.

7C024–14

7C024–15

7C024–16

9

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