CY7C0241(1999) Ver la hoja de datos (PDF) - Cypress Semiconductor

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CY7C0241
(Rev.:1999)

4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with Sem, Int, Busy

Cypress Semiconductor 

CY7C024/0241

CY7C025/0251

v

Logic Block Diagram

R/WL

UB L

LB L

CE L

OE L

R/WR

UBR

LBR

CER

OE R

[3]

I/O 8L – I/O 15L

I/O

0L

–

I/O

[2]

7L

[1]

BUSYL

(CY7C025/0251) A12L

A11L

A0L

I/O

CONTROL

I/O

CONTROL

ADDRESS

DECODER

MEMORY

ARRAY

ADDRESS

DECODER

R/W L

SEM L

INT L

CE L

OE L

UB L

LB L

Notes:

1. BUSY is an output in master mode and an input in slave mode.

2. I/O0 –I/O8 on the CY7C0241/0251.

3. I/O9 –I/O17 on the CY7C0241/0251.

INTERRUPT

SEMAPHORE

ARBITRATION

M/S

CE R

OE R

UB R

LB R

I/O8R – I/O15R [3]

I/O 0R– I/O 7R [2]

[1]

BUSYR

A12R (CY7C025/0251)

A11R

A0R

R/W R

SEM R

INTR

7C024–1

2

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