IR3Y48A1 Ver la hoja de datos (PDF) - Sharp Electronics

Número de pieza

componentes Descripción

Fabricante

IR3Y48A1

CCD Signal Process & Digital Interface IC

Sharp Electronics 

Clamp Circuits

DC CLAMP

DC level of the CCDIN/REFIN input is fixed by

internal DC clamp circuit. DC level of C-coupled

CCD signal at the CDS input is set to CLPCAP by

IR3Y48A1

the internal DC clamp circuit.

Normally clamp switches are turned on at the black

level calibration period. Place 0.1 µF external

capacitance between CLPCAP and AVSS.

DC Clamp

SHR SHD CCDCLP

REFIN

Timing Control

(Register Conditions)

Clamp Timing

CCD

ADCK

CCD

CCDIN

Clamp

(CCDCLP) Source

CCDCLP

CLPCAP

DC Clamp Function

REFIN, CCDIN

CLPCAP Clamp Level

CLPCAP Level

NOTE : For ADIN input, clamp operation is controlled by ADCLP.

(Black level calibration is performed at the same time.)

CLAMP OF THE ADIN SIGNAL

Clamp operation for the ADIN path is also available.

Note that clamp voltage [CLPCAP] is different

between CCDIN/REFIN input and the ADIN input.

Clamp operation of ADIN signal can be turned off

by register setting.

Clamp circuit is controlled by ADCLP signal at

"ADIN signal to ADC" mode. Black level calibration

circuit is also controlled by ADCLP at "ADIN signal

to PGA" mode.

CLAMP CONTROL

Following items are selectable by the register setting.

a) Clamp current [Mode (2) Register D7]

Normal or fast clamp is selectable for charge

current. (Select normal clamp in general.)

b) Clamp target [Mode (2) Register D5 & D4]

Input signals (REFIN and CCDIN) to be

clamped are selectable. It is also possible to

turn off the clamp function.

ADIN DC Clamp

ADCLP

Timing Control

ADIN

To PGA

or

To ADC

(ADCLP)

CLPCAP

ADIN DC Clamp Function

8

Share Link: