IR3Y48A1 Ver la hoja de datos (PDF) - Sharp Electronics

Número de pieza

componentes Descripción

Fabricante

IR3Y48A1

CCD Signal Process & Digital Interface IC

Sharp Electronics 

Gain Control Circuit

The total gain for a CCD input signal covers from

–1.94 to +36 dB.

This range consists of CDS (0/6/12/–1.94 dB), PGA

IR3Y48A1

rough (0/6/12/18 dB), and PGA fine (0 to 6 dB

(0.047 dB/step)). The CDS gain is controlled by a

2-bit register and the PGA gain is controlled by a 9-

bit register.

PGA Gain Control

24 dB

0 dB

000

Total Gain

Total Gain

36 dB

0.047 dB

1 step

30 dB

24 dB

18 dB

CDS gain = 12 dB

(D5 = 1, D4 = 0)

CDS gain = 6 dB

(D5 = 0, D4 = 1)

CDS gain = 0 dB

(D5 = 0, D4 = 0)

CDS gain = –1.94 dB

(D5 = 1, D4 = 1)

12 dB

6 dB

511 (Decimal)

0 dB

–1.94 dB

000

PGA Gain Setting

511 (Decimal)

CDS Gain

Mode (3)

Register

(D5 & D4)

0/6/12/–1.94 dB

PGA Gain

Rough

(0/6/12/18 dB)

Fine

0.047 dB/Step

(0 to 6 dB)

to

ADC

CCDIN

ADIN (PGAIN)

Total Gain = –1.94 to +35.91 dB

NOTE :

• The gain of the ADIN (PGA) input pass can be set from 0 to 24 dB.

Gain Control

11

Share Link: