X2804CP-15 Ver la hoja de datos (PDF) - Xicor -> Intersil

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X2804CP-15

5 Volt, Byte Alterable E2PROM

Xicor -> Intersil 

X2804C

CE Controlled Write Cycle

ADDRESS

CE

OE

WE

DATA IN

tAS

tOES

tCS

tDV

DATA OUT

tWC

tAH

tCW

tOEH

tCH

DATA VALID

tDS

tDH

HIGH Z

Page Mode Write Cycle

6612 FHD F06

OE (6)

CE

WE

ADDR.* (7)

tWP

tBLC

tWPH

I/O

BYTE 0

BYTE 1

BYTE 2

BYTE n

BYTE n+1

*For each successive write within the page write operation, A4–A10 should be the same or

writes to an unknown address could occur.

LAST BYTE

BYTE n+2

tWC

6612 FHD F07.1

Notes: (6) Between successive byte writes within a page write operation, OE can be strobed LOW: e.g. this can be done with CE and WE

HIGH to fetch data from another memory device within the system for the next write; or with WE HIGH and CE LOW effectively

performing a polling operation.

(7) The timings shown above are unique to page write operations. Individual byte load operations within the page write must conform

to either the CE or WE controlled write cycle timing.

9

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