(Advance Version)
IP178A
PIN Description (continued)
Pin no.
Label
Type
External MII port operation parameter setting
135
MII_P0_EXT_EN IPL External MII port enable
1: enable, 0: disable (default)
Description
154
MII_P0_FULL IPH Duplex setting of external MII port
1: full (default), 0: half
It is valid only if MII_P0_EXT_EN is set to logic high.
153
MII_P0_SPEED IPH Speed setting of external MII port
1: 10M (default), 0: 100M
It is valid only if MII_P0_EXT_EN is set to logic high.
136 MII_P0_FLOW_CTL IPL Flow control setting of external MII port
1: on, 0: off (default)
It is valid only if MII_P0_EXT_EN is set to logic high.
127
MII_P0_SNI
IPL External Mac interface selection
1: SNI interface
0: MII interface (default)
It is valid only if MII_P0_EXT_EN is set to logic high. If the SNI interface is
enabled, port0 of switch core is forced to 10Mbps.
Power
BGVCC
BGGND
PLLGND
PLLVCC
OSCGND
OSCVCC
GND
VCC
GND_SRAM
VCC_SRAM
GND_IO
VCC_IO
RXVCC0~7
RXGND0~7
TXGND0~7
TXVCC01
TXVCC23
TXVCC45
TXVCC67
NC
I Power of band gap circuit
I Power of band gap circuit
I Power of PLL circuit
I Power of PLL circuit
I Power of oscillator
I Power of oscillator
I Power of internal logic
I Power of internal logic
I Power of internal SRAM
I Power of internal SRAM
I Power for LED and EEPROM
I Power for LED and EEPROM
I Power of analog receive block
I Power of analog receive block
I Power of analog transmit buffer
I Power of analog transmit buffer
No connection. They should be left open for normal operation.
Preliminary, Specification subject to change without notice 16
IP178A-DS-P05
Sep. 09, 2002