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INTEL386

Intel386 SX MICROPROCESSOR

Intel 

Intel386TM SX MICROPROCESSOR

An Intel386 SX Microprocessor operating system

can provide a Virtual 8086 Environment which is to-

tally transparent to the application software by inter-

cepting and then emulating 8086 operating system’s

calls and intercepting IN and OUT instructions

Entering and Leaving Virtual 8086 Mode

Virtual 8086 mode is entered by executing a 32-bit

IRET instruction at CPLe0 where the stack has a 1

in the VM bit of its EFLAGS image or a Task Switch

(at any CPL) to a Intel386 SX Microprocessor task

whose Intel386 SX CPU TSS has a EFLAGS image

containing a 1 in the VM bit position while the proc-

essor is executing in the Protected Mode POPF

does not affect the VM bit but a PUSHF always

pushes a 0 in the VM bit

The transition out of Virtual 8086 mode to protected

mode occurs only on receipt of an interrupt or ex-

ception In Virtual 8086 mode all interrupts and ex-

ceptions vector through the protected mode IDT

and enter an interrupt handler in protected mode As

part of the interrupt processing the VM bit is cleared

Because the matching IRET must occur from level 0

Interrupt or Trap Gates used to field an interrupt or

exception out of Virtual 8086 mode must perform an

inter-level interrupt only to level 0 Interrupt or Trap

Gates through conforming segments or through

segments with DPLl0 will raise a GP fault with the

CS selector as the error code

Task Switches To From Virtual 8086 Mode

Tasks which can execute in Virtual 8086 mode must

be described by a TSS with the Intel386 SX CPU

format (type 9 or 11 descriptor) A task switch out of

virtual 8086 mode will operate exactly the same as

any other task switch out of a task with a Intel386 SX

CPU TSS All of the programmer visible state includ-

ing the EFLAGS register with the VM bit set to 1 is

stored in the TSS The segment registers in the TSS

will contain 8086 segment base values rather than

selectors

A task switch into a task described by a Intel386 SX

CPU TSS will have an additional check to determine

if the incoming task should be resumed in Virtual

8086 mode Tasks described by 286 format TSSs

cannot be resumed in Virtual 8086 mode so no

check is required there (the FLAGS image in 286

format TSS has only the low order 16 FLAGS bits)

Before loading the segment register images from a

Intel386 SX CPU TSS the FLAGS image is loaded

so that the segment registers are loaded from the

TSS image as 8086 segment base values The task

is now ready to resume in Virtual 8086 mode

Transitions Through Trap and Interrupt Gates

and IRET

A task switch is one way to enter or exit Virtual 8086

mode The other method is to exit through a Trap or

Interrupt gate as part of handling an interrupt and

to enter as part of executing an IRET instruction

The transition out must use a Intel386 SX CPU Trap

Gate (Type 14) or Intel386 SX CPU Interrupt Gate

(Type 15) which must point to a non-conforming lev-

el 0 segment (DPLe0) in order to permit the trap

handler to IRET back to the Virtual 8086 program

The Gate must point to a non-conforming level 0

segment to perform a level switch to level 0 so that

the matching IRET can change the VM bit Intel386

SX CPU gates must be used since 286 gates save

only the low 16 bits of the EFLAGS register (the VM

bit will not be saved) Also the 16-bit IRET used to

terminate the 286 interrupt handler will pop only the

lower 16 bits from FLAGS and will not affect the VM

bit The action taken for a Intel386 SX CPU Trap or

Interrupt gate if an interrupt occurs while the task is

executing in virtual 8086 mode is given by the follow-

ing sequence

1 Save the FLAGS register in a temp to push later

Turn off the VM TF and IF bits

2 Interrupt and Trap gates must perform a level

switch from 3 (where the Virtual 8086 Mode pro-

gram executes) to level 0 (so IRET can return)

3 Push the 8086 segment register values onto the

new stack in this order GS FS DS ES These

are pushed as 32-bit quantities Then load these 4

registers with null selectors (0)

4 Push the old 8086 stack pointer onto the new

stack by pushing the SS register (as 32-bits) then

pushing the 32-bit ESP register saved above

5 Push the 32-bit EFLAGS register saved in step 1

6 Push the old 8086 instruction onto the new stack

by pushing the CS register (as 32-bits) then push-

ing the 32-bit EIP register

7 Load up the new CS EIP value from the interrupt

gate and begin execution of the interrupt routine

in protected mode

The transition out of V86 mode performs a level

change and stack switch in addition to changing

back to protected mode Also all of the 8086 seg-

ment register images are stored on the stack (be-

hind the SS ESP image) and then loaded with null

(0) selectors before entering the interrupt handler

This will permit the handler to safely save and re-

store the DS ES FS and GS registers as 286 selec-

tors This is needed so that interrupt handlers which

don’t care about the mode of the interrupted pro-

gram can use the same prologue and epilogue code

for state saving regardless of whether or not a ‘na-

tive‘ mode or Virtual 8086 Mode program was inter-

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