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INTEL386

Intel386 SX MICROPROCESSOR

Intel 

Intel386TM SX MICROPROCESSOR

Several instructions particularly those applying to

the multitasking and the protection model are avail-

able only in Protected Mode Therefore attempting

to execute the following instructions in Real Mode or

in Virtual 8086 Mode generates an exception 6 fault

LTR

LLDT

LAR

LSL

ARPL

STR

SLDT

VERR

VERW

The instructions which are IOPL sensitive in Protect-

ed Mode are

IN

STI

OUT CLI

INS

OUTS

REP INS

REP OUTS

In Virtual 8086 Mode the following instructions are

IOPL-sensitive

INT n STI

PUSHF CLI

POPF IRET

The PUSHF POPF and IRET instructions are IOPL-

sensitive in Virtual 8086 Mode only This provision

allows the IF flag to be virtualized to the virtual 8086

Mode program The INT n software interrupt instruc-

tion is also IOPL-sensitive in Virtual 8086 mode

Note that the INT 3 INTO and BOUND instructions

are not IOPL-sensitive in Virtual 8086 Mode

The I O instructions that directly refer to addresses

in the processor’s I O space are IN INS OUT and

OUTS The Intel386 SX Microprocessor has the abil-

ity to selectively trap references to specific I O ad-

dresses The structure that enables selective trap-

ping is the I O Permission Bit Map in the TSS seg-

ment (see Figures 4 8 and 4 9) The I O permission

map is a bit vector The size of the map and its loca-

tion in the TSS segment are variable The processor

locates the I O permission map by means of the I O

map base field in the fixed portion of the TSS The

I O map base field is 16 bits wide and contains the

offset of the beginning of the I O permission map

In protected mode when an I O instruction (IN INS

OUT or OUTS) is encountered the processor first

checks whether CPLsIOPL If this condition is true

the I O operation may proceed If not true the proc-

essor checks the I O permission map (in Virtual

8086 Mode the processor consults the map without

regard for the IOPL)

Each bit in the map corresponds to an I O port byte

address for example the bit for port 41 is found at

I O map base a5 bit offset 1 The processor tests

all the bits that correspond to the I O addresses

spanned by an I O operation for example a double

word operation tests four bits corresponding to four

adjacent byte addresses If any tested bit is set the

processor signals a general protection exception If

all the tested bits are zero the I O operations may

proceed

It is not necessary for the I O permission map to

represent all the I O addresses I O addresses not

spanned by the map are treated as if they had one-

bits in the map The I O map base should be at

least one byte less than the TSS limit the last byte

beyond the I O mapping information must contain

all 1’s

Because the I O permission map is in the TSS seg-

ment different tasks can have different maps Thus

the operating system can allocate ports to a task by

changing the I O permission map in the task’s TSS

IMPORTANT IMPLEMENTATION NOTE Beyond

the last byte of I O mapping information in the I O

permission bit map must be a byte containing all 1’s

The byte of all 1’s must be within the limit of the

Intel386 SX CPU TSS segment (see Figure 4 8)

Interrupt Handling

In order to fully support the emulation of an 8086

machine interrupts in Virtual 8086 Mode are han-

dled in a unique fashion When running in Virtual

Mode all interrupts and exceptions involve a privi-

lege change back to the host Intel386 SX Microproc-

essor operating system The Intel386 SX Microproc-

essor operating system determines if the interrupt

comes from a Protected Mode application or from a

Virtual Mode program by examining the VM bit in the

EFLAGS image stored on the stack

When a Virtual Mode program is interrupted and ex-

ecution passes to the interrupt routine at level 0 the

VM bit is cleared However the VM bit is still set in

the EFLAG image on the stack

The Intel386 SX Microprocessor operating system in

turn handles the exception or interrupt and then re-

turns control to the 8086 program The Intel386 SX

Microprocessor operating system may choose to let

the 8086 operating system handle the interrupt or it

may emulate the function of the interrupt handler

For example many 8086 operating system calls are

accessed by PUSHing parameters on the stack and

then executing an INT n instruction If the IOPL is set

to 0 then all INT n instructions will be intercepted by

the Intel386 SX Microprocessor operating system

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