IN74AC112N Ver la hoja de datos (PDF) - Integral Corp.

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IN74AC112N

Dual J-K Flip-Flop with Set and Reset High-Speed Silicon-Gate CMOS

Integral Corp. 

TECHNICAL DATA

Dual J-K Flip-Flop

with Set and Reset

High-Speed Silicon-Gate CMOS

IN74AC112

The IN74AC112 is identical in pinout to the LS/ALS112,

HC/HCT112. The device inputs are compatible with standard CMOS

outputs; with pullup resistors, they are compatible with LS/ALS

outputs.

Each flip-flop is negative-edge clocked and has active-low

asynchronous Set and Reset inputs.

• Outputs Directly Interface to CMOS, NMOS, and TTL

• Operating Voltage Range: 2.0 to 6.0 V

• Low Input Current: 1.0 µA; 0.1 µA @ 25°C

• High Noise Immunity Characteristic of CMOS Devices

• Outputs Source/Sink 24 mA

ORDERING INFORMATION

IN74AC112N Plastic

IN74AC112D SOIC

TA = -40° to 85° C for all

packages

PIN ASSIGNMENT

LOGIC DIAGRAM

PIN 16=VCC

PIN 8 = GND

FUNCTION TABLE

Inputs

Outputs

Set Reset Clock J K Q

Q

L

H

X

XX H

L

H

L

L

L

X

XX L

H

X

XX

L*

L*

H

H

L L No Change

H

H

LH L

H

H

H

HL H

L

H

H

HH

Toggle

H

H

L

X X No Change

H

H

H

X X No Change

H

H

X X No Change

* Both outputs will remain low as long as Set and Reset are

low, but the output states are unpredictable if Set and Reset

go high simultaneously

X = Don’t Care

127

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