IN24LC16 Ver la hoja de datos (PDF) - Integral Corp.

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Fabricante

IN24LC16

16K SERIAL EEPROM WITH I2C BUS

Integral Corp. 

IN24LC16

The 24LC16B employs a VCC threshold detector circuit which disables the internal erase/write logic if the

VCC is below 1.5 volts at nominal conditions.

The SCL and SDA inputs have Schmitt trigger and filter circuits which suppress noise spikes to assure

proper device operation even on a noisy bus.

CURRENT ADDRESS READ

RANDOM READ

: SEQUENTIAL READ

PIN DESCRIPTIONS

SDA Serial Address/Data Input/Output

This is a Bi-directional pin used to transfer addresses and data into and data out of the device. It is an open

drain terminal, therefore the SDA bus requires a pullup resistor to VCC (typical 10K for 100 kHz, 2 K for

400 kHz).

For normal data transfer SDA is allowed to change only during SCL low. Changes during SCL high are

reserved for indicating the

SCL Serial Clock

This input is used to synchronize the data transfer from and to the device.

WP

This pin must be connected to either VSS or VCC.

If tied to Vss normal memory operation is enabled (read/write the entire memory 000-7FF).

If tied to VCC, WRITE operations are inhibited. The entire memory will be write-protected. Read operations

are not affected.

This feature allows the user to use the 24LC16B as a serial ROM when WP is enabled (tied to VCC).

A0, A1, A2

These pins are not used by the 24LC16B. They may be left floating or tied to either VSS or VCC.

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