IDTCV140 Ver la hoja de datos (PDF) - Integrated Device Technology
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IDTCV140 Datasheet PDF : 26 Pages
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IDTCV140
PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR
COMMERCIAL TEMPERATURE RANGE
PIN DESCRIPTION
Pin Number
Name
Type
1
VDD_PCI
PWR
2
VSS_PCI
GND
3
PCI1
OUT
4
PCI2
OUT
5
PCI3
OUT
6
VSS_PCI
GND
7
VDD_PCI
PWR
8
PCIF0/ITP_EN
I/O
9
PCIF1/SEL100/96#
I/O
10
VTT_PWRGD#/PD
IN
11
VDD48
PWR
12
USB48/FSA
I/O
13
VSS48
GND
14
DOT96
OUT
15
DOT96#
OUT
16
FSB
IN
17
LVDS
OUT
18
LVDS#
OUT
19
SRC1
OUT
20
SRC1#
OUT
21
VDD_SRC
PWR
22
SRC2
OUT
23
SRC2#
OUT
24
SRC3
OUT
25
SRC3#
OUT
26
SRC4
OUT
27
SRC4#
OUT
28
VDD_SRC
PWR
29
VSS_SRC
GND
30
SRC5#
OUT
31
SRC5
OUT
32
SRC_6#/CLKREQB#
IN
33
SRC_6/CLKREQA#
IN
34
VDD_SRC
PWR
35
CPU2_ITP#/SRC7#
OUT
36
CPU2_ITP/SRC7
OUT
37
VDDA
PWR
38
VSSA
GND
39
IREF
OUT
40
CPU1#
OUT
41
CPU1
OUT
42
VDD_CPU
PWR
Description
3.3V
GND
PCI clock
PCI clock
PCI clock
GND
3.3V
PCI clock, free running. CPU2 select (sampled on VTT_PWRGD# assertion) HIGH = CPU2.
PCI clock, free running. SEL100/96MHz (sampled on VTT_PWRGD# assertion) HIGH, LVDS = 100MHz.
Level-sensitive strobe used to latch the FSA, FSB, FSC/TEST_SEL, and PCIF0/ITP_EN inputs. After
VTT_PWRGD# assertion, becomes a real-time input for asserting power down. (Active HIGH)
3.3V
48MHz clock for CPU frequency selection
GND
96MHz 0.7 current mode differential clock output
96MHz 0.7 current mode differential clock output
CPU frequency selection. Selects REF/N or Hi-Z when in test mode, Hi-Z = 1, REF/N = 0.
Differential serial reference clock
Differential serial reference clock
Differential serial reference clock
Differential serial reference clock
3.3V
Differential serial reference clock
Differential serial reference clock
Differential serial reference clock
Differential serial reference clock
Differential serial reference clock
Differential serial reference clock
3.3V
GND
Differential serial reference clock
Differential serial reference clock
SRC clock enable (Active LOW, see Bytes 10 and 11) / SRC_6# CLK, mode selected by pin 56
SRC clock enable (Active LOW, see Bytes 10 and 11) / SRC_6 CLK, mode selected by pin 56
3.3V
Selectable CPU or SRC differential clock output. ITP_EN = 0 at VTT_PWRGD# assertion = SRC7#.
Selectable CPU or SRC differential clock output. ITP_EN = 0 at VTT_PWRGD# assertion = SRC7.
3.3V
GND
Reference current for differential output buffer
Host 0.7 current mode differential clock output
Host 0.7 current mode differential clock output
3.3V
3
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