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IDT821064

QUAD PROGRAMMABLE PCM CODEC WITH GCI INTERFACE

Integrated Device Technology 

IDT821064 QUAD PROGRAMMABLE PCM CODEC WITH GCI INTERFACE

INDUSTRIAL TEMPERATURE RANGE

two consecutive frames), it is able to check for data errors. If two different

bytes are received the receiver will wait for the receipt of two identical

successive bytes (last look function).

A collision resolution mechanism ( check if another device is trying to

send data during the same time) is implemented in the transmitter. This

is done by looking for the inactive (‘1’) phase of the MX bit and making a

per bit collision check on the transmitted monitor data ( check if transmitted

‘1’s are on DU/DD line; DU/DD line are open drain lines).

Any abort leads to a reset of the IDT821064 command stack, the

device is ready to receive new commands.

To obtain a maximum speed data transfer, the transmitter anticipates

the falling edge of the receivers acknowledgment.

Due to the inherent programming structure, duplex operation is not

possible. It is not allowed to send any data to the IDT821064, while

transmission is active.

Refer to Figure 4 and 5 for more information about monitor handshake

procedure.

The IDT821064 can be controlled very flexibly by commands operating

on registers or RAM via the GCI monitor channel, refer to “Programming

Description” for further details.

Master Device

MX

Monitor

Transmitter MR

DD

DU

MR

Monitor

Receiver

MX

IDT821064

MX

Monitor

MR

Receiver

MR

Monitor

MX

Transmitter

Figure 3. Monitor Channel Operation

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