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IDT821054A

QUAD PROGRAMMABLE PCM CODEC WITH MPI INTERFACE

Integrated Device Technology 

IDT821054A QUAD PROGRAMMABLE PCM CODEC WITH MPI INTERFACE

INDUSTRIAL TEMPERATURE

2 FUNCTIONAL DESCRIPTION

The IDT821054A is a four-channel PCM CODEC with on-chip digital

filters. It provides a four-wire solution for the subscriber line circuitry in

digital switches. The IDT821054A converts analog voice signals to

digital PCM samples and digital PCM samples back to analog voice

signals. The digital filters are used to bandlimit the voice signals during

conversion. High performance oversampling Analog-to-Digital

Converters (ADC) and Digital-to-Analog Converters (DAC) in the

IDT821054A provide the required conversion accuracy. The associated

decimation and interpolation filtering is performed by both dedicated

hardware and Digital Signal Processor (DSP). The DSP also handles all

other necessary procession such as PCM bandpass filtering, sample

rate conversion and PCM companding.

2.1 MPI/PCM INTERFACE

A serial Microprocessor Interface (MPI) is provided for the master

device to control the IDT821054A. Two PCM buses are provided to

transfer the digital voice data.

2.1.1 MICROPROCESSOR INTERFACE (MPI)

The internal configuration registers (local/global), the SLIC signaling

interface and the Coefficient-RAM of the IDT821054A are programmed

by the master device via MPI, which consists of four lines (pins): CCLK,

CS, CI and CO. All commands and data are aligned in byte (8 bits) and

transferred via the MPI interface. CCLK is the clock of the MPI interface.

The frequency of CCLK can be up to 8.192 MHz. CS is the chip

selection pin. A low level on CS enables the MPI interface. CI and CO

are data input and data output pins, carrying control commands and

data bytes to/from the IDT821054A.

The data transfer is synchronized to the CCLK signal. The contents

of CI is latched on the rising edges of CCLK, while CO changes on the

falling edges of CCLK. The CCLK signal is the only reference of CI and

CO pins. Its duty and frequency may not necessarily be standard.

When the CS pin becomes low, the IDT821054A treats the first byte

on the CI pin as command and the rest as data. To write another

command, the CS pin must be changed from low to high to finish the

previous command and then changed from high to low to indicate the

start of a new command. When a read/write operation is completed, the

CS pin must be set to high in 8-bit time.

During the execution of commands that are followed by output data

byte(s), the IDT821054A will not accept any new commands from the CI

pin. But the data transfer sequence can be interrupted by setting the CS

pin to high at any time. See Figure - 1 and Figure - 2 for examples of

MPI write and read operation timing diagrams.

CCLK

CS

CI

765432107654321076543210

CO

High 'Z'

Command Byte

Data Byte 1

Figure - 1 An Example of the MPI Interface Write Operation

Data Byte 2

CCLK

CS

CI

76543210

Command Byte

Ignored

Identification Code

Data Byte 1

CO

High 'Z'

'1' '0' '0' '0' '0' '0' '0' '1' 7 6 5 4 3 2 1 0

Figure - 2 An Example of the MPI Interface Read Operation (ID = 81H)

9

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