IDT821054A Ver la hoja de datos (PDF) - Integrated Device Technology
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IDT821054A Datasheet PDF : 42 Pages
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IDT821054A QUAD PROGRAMMABLE PCM CODEC WITH MPI INTERFACE
INDUSTRIAL TEMPERATURE
Name
TSX1
TSX2
CS
CI
CO
CCLK
MCLK
RESET
INT12
INT34
CHCLK1
CHCLK2
Type Pin Number
Description
0
25
28
Transmit Output Indicator.
The TSX1 pin becomes low when PCM data is transmitted via DX1. Open-drain.
The TSX2 pin becomes low when PCM data is transmitted via DX2. Open-drain.
I
17
Chip Selection.
A logic low level on this pin enables the Serial Control Interface.
I
19
Serial Control Interface Data Input.
Control data input pin. CCLK determines the data rate.
Serial Control Interface Data Output.
O
20
Control data output pin. CCLK determines the data rate. This pin is in high-impedance state when the CS
pin is logic high.
I
18
Serial Control Interface Clock.
This is the clock for the Serial Control Interface. It can be up to 8.192 MHz.
Master Clock Input.
I
22 This pin provides the clock for the DSP of the IDT821054A. The frequency of the MCLK can be 1.536
MHz, 1.544 MHz, 2.048 MHz, 3.072 MHz, 3.088 MHz, 4.096 MHz, 6.144 MHz, 6.176 MHz or 8.192 MHz.
I
23
Reset Input.
Forces the device to default mode. Active low.
Interrupt Output Pin for Channel 1-2.
O
34 Active high interrupt signal for Channel 1 and 2, open-drain. It reflects the changes on the corresponding
SLIC input pins.
Interrupt Output Pin for Channel 3-4.
O
15 Active high interrupt signal for Channel 3 and 4, open-drain. It reflects the changes on the corresponding
SLIC input pins.
O
33
Chopper Clock Output One.
Provides a programmable output signal (2 -28 ms) synchronous to MCLK.
O
16
Chopper Clock Output Two.
Provides a programmable output signal (256 kHz, 512 kHz or 16.384 MHz) synchronous to MCLK.
8
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