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IDT821054A

QUAD PROGRAMMABLE PCM CODEC WITH MPI INTERFACE

Integrated Device Technology 

IDT821054A QUAD PROGRAMMABLE PCM CODEC WITH MPI INTERFACE

1 PIN DESCRIPTION

INDUSTRIAL TEMPERATURE

Name

GNDA1

GNDA2

GNDA3

GNDA4

GNDD

VDDA12

VDDA34

VDDD

VDDB

CNF

VIN1-4

VOUT1-4

SI1_(1-4)

SI2_(1-4)

SB1_(1-4)

SB2_(1-4)

SB3_(1-4)

SO1_(1-4)

SO2_(1-4)

DX1

DX2

DR1

DR2

FS

BCLK

Type Pin Number

Description

Ground

50

54 Analog Ground.

59 All ground pins should be connected together.

63

Ground

21

Digital Ground.

All digital signals are referred to this pin.

Power

52

61

+5 V Analog Power Supply.

These pins should be connected to ground via a 0.1 µF capacitor. All power supply pins should be

connected together.

Power

24 +5 V Digital Power Supply.

Power

+5 V Analog Power Supply.

57 This pin should be connected to ground via a 0.1 µF capacitor. All power supply pins should be connected

together.

−

56

Capacitor Noise Filter.

This pin should be connected to ground via a 0.22 µF capacitor.

I

49,

55,

58,

64

Analog Voice Inputs of Channel 1-4.

These pins should be connected to the

corresponding

SLIC

via

a

0.22

µF

capacitor.

O

51,

53, 60,

62

Voice Frequency Receiver

These pins can drive 300 Ω

Outputs

AC load.

of Channel 1-4.

It can drive transformers

directly.

I

36, 47, 2, 13

35, 48, 1, 14

SLIC Signalling Inputs with debounce function for Channel 1-4.

I/O

39, 44, 5, 10

38, 45, 4, 11

37, 46, 3, 12

Bi-directional SLIC Signalling I/Os for Channel 1-4.

These pins can be individually programmed as input or output.

O

41, 42, 7, 8

40, 43, 6, 9

SLIC Signalling Outputs for Channel 1-4.

Transmit PCM Data Output, PCM Highway One.

O

26 Transmit PCM Data to PCM highway one. The PCM data is output through DX1 or DX2 as selected by

local register LREG5. This pin remains in high-impedance state until a pulse appears on the FS pin.

Transmit PCM Data Output, PCM Highway Two.

O

29 Transmit PCM Data to PCM highway two. The PCM data is output thought DX1 or DX2 as selected by

local register LREG5. This pin remains in high-impedance state until a pulse appears on the FS pin.

Receive PCM Data Input, PCM Highway One.

I

27 The PCM data is received from PCM highway one (DR1) or two (DR2). The receive PCM highway is

selected by local register LREG6.

Receive PCM Data Input, PCM Highway Two.

I

30 The PCM data is received from PCM highway one (DR1) or two (DR2). The receive PCM highway is

selected by local register LREG6.

I

31

Frame Synchronization.

FS is an 8 kHz synchronization clock that identifies the beginning of the PCM frame.

Bit Clock.

I

32 This pin clocks out the PCM data to DX1 or DX2 pin and clocks in PCM data from DR1 or DR2 pin. It may

vary from 512 kHz to 8.192 MHz and should be synchronous to FS.

7

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