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IDT821054A

QUAD PROGRAMMABLE PCM CODEC WITH MPI INTERFACE

Integrated Device Technology 

IDT821054A QUAD PROGRAMMABLE PCM CODEC WITH MPI INTERFACE

INDUSTRIAL TEMPERATURE

2.2 DSP PROGRAMMING

2.2.1 SIGNAL PROCESSING

Several blocks are programmable for signal processing. This allows

users to optimize the performance of the IDT821054A for the system.

Figure - 4 shows the signal flow for each channel and indicates the

programmable blocks.

The programmable digital filters are used to adjust gain and

impedance, balance transhybrid and correct frequency response. All the

coefficients of the digital filters can be calculated automatically by a

software provided by IDT. When users provide accurate SLIC model,

impedance and gain requirements, this software will calculate all the

coefficients automatically. After loading these coefficients to the

coefficient RAM of the IDT821054A, the final AC characteristics of the

line card (consists of SLIC and CODEC) will meet the ITU-T

specifications.

Analog

@2 MHz

VIN

LPF/AA ∑ −∆

Transmit Path

@64 KHz

@16 KHz

LREG1: CS[3]

CS[3] = 1: enable (normal)

CS[3] = 0: disable (bypass)

@8 KHz

TS

Level Meter

PCM Highway

D1

GTX

D2

LPF FRX

HPF

CMP

TSA

DX1/DX2

GIS

IMF ECF

VOUT

LPF/SC

∑ −∆

U1 UF

GRX U2 LPF

FRR

LREG1: CS[2]

CS[2] = 1: enable (normal)

CS[2] = 0: disable (cut)

LREG1: CS[0]

CS[0] = 1: enable (normal)

CS[0] = 0: disable (cut)

LREG1: CS[1]

CS[1] = 1: enable (normal)

CS[1] = 0: disable (cut)

Receive Path

EXP

TSA

CUT-OFF-PCM

Dual Tone

DR1/DR2

Bold Black Framed: Programmable Filters

Fine Black Framed: Fixed Filters

Abbreviation List:

LPF/AA: Anti-Alias Low-pass Filter

LPF/SC: Smoothing Low-pass Filter

LPF: Low-pass Filter

HPF: High-pass Filter

GIS: Gain for Impedance Scaling

D1: 1st Down Sample Stage

D2: 2nd Down Sample Stage

U1: 1st Up Sample Stage

U2: 2nd Up Sample Stage

UF: Up Sampling Filter (64 k - 128 k)

Figure - 4 Signal Flow for Each Channel

IMF: Impedance Matching Filter

ECF: Echo Cancellation Filter

GTX: Gain for Transmit Path

GRX: Gain for Receive Path

FRX: Frequency Response Correction for Transmit

FRR: Frequency Response Correction for Receive

CMP: Compression

EXP: Expansion

TSA: Time Slot Assignment

2.2.2 GAIN ADJUSTMENT

For each individual channel, the analog A/D gain in the transmit path

can be selected as 0 dB or 6 dB. The selection is done by the GAD bit in

LREG9. It is 0 dB by default.

For each individual channel, the analog D/A gain in the receive path

can be selected as 0 dB or -6 dB. The selection is done by the GDA bit

in LREG9. It is 0 dB by default.

For each channel, the digital gain filter in the transmit path (GTX) can

be disabled by setting the CS[5] bit in LREG1 to ‘0’. If the CS[5] bit in

LREG1 is set to ‘1’, the GTX filter will be enabled and the digital gain will

be programmed by the coefficient RAM. Note that the RAM block for

containing GTX coefficient is shared by all four channels. That is, once

the GTX coefficient is written to the coe-RAM, it will be used by all four

channels. The GTX is programmable from -3 dB to +12 dB with

minimum 0.1 dB step.

For each channel, the digital gain filter in the receive path (GRX) can

be disabled by setting the CS[7] bit in LREG1 to ‘0’. If the CS[7] bit in

LREG1 is set to ‘1’, the GRX filter will be enabled and the digital gain will

be programmed by the coefficient RAM. Note that the RAM block for

containing GRX coefficient is shared by all four channels. That is, once

the GRX coefficient is written to the coe-RAM, it will be used by all four

channels. The GRX is programmable from -12 dB to +3 dB with

minimum 0.1 dB step.

2.2.3 IMPEDANCE MATCHING

The IDT821054A provides a programmable feedback path from VIN

to VOUT for each channel. This feedback synthesizes the two-wire

impedance of the SLIC. The programmable Impedance Matching Filter

11

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