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IDT7M1002S30G

16K x 32 CMOS DUAL-PORT STATIC RAM MODULE

Integrated Device Technology 

IDT7M1002

16K x 32 CMOS DUAL-PORT STATIC RAM MODULE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TIMING WAVEFORM OF SEMAPHORE READ AFTER WRITE, EITHER SIDE(1)

A0–A2

tAW

VALID ADDRESS

tWR

tAA

VALID ADDRESS

SEM

tWP

tSOP

tACE

tDW

DATA0

DATAIN VALID

R/ W

tAS

tWP

tDH

tSWRD

tAOE

OE

tSOP

WRITE CYCLE

NOTE:

1. CS ≥ VIH for the duration of the above timing (both write and read cycle).

READ CYCLE

tOH

DATAOUT

VALID

2795 drw 09

TIMING WAVEFORM OF SEMAPHORE CONTENTION(1, 3, 4)

(2)

SIDE "A"

A0A — A2A

R/ WA

MATCH

SEMA

(2)

SIDE "B"

A0B — A2B

R/ WB

tSPS

MATCH

SEMB

2795 drw 10

NOTES:

1. DOR = DOL ≤ VIL, (L_ CS = R_ CS) ≥ VIH Semaphore Flag is released from both sides (reads as ones from both sides) at cycle start.

2. “A” may be either left or right port. “B” is the opposite port from “A”.

3. This parameter is measured from R/WA or SEMA going HIGH to R/WB or SEMB going HIGH.

4. If tSPS is violated, the semaphore will fall positively to one side or the other, but there is no guarantee which side will obtain the flag.

7.02

8

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