IDT7M1002S30G Ver la hoja de datos (PDF) - Integrated Device Technology
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IDT7M1002S30G Datasheet PDF : 12 Pages
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IDT7M1002
16K x 32 CMOS DUAL-PORT STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF WRITE CYCLE NO. 1 (R/W CONTROLLED TIMING)(1, 2, 4)
ADDRESS
OE
CS
R/ W
DATAOUT
DATAIN
tAS (6)
(4)
tWC
tAW
tWP (2)
tWHZ (9)
tCHZ (9)
tWR (7)
t OW (9)
tDW
tDH
DATA VALID
(4)
2795 drw 07
TIMING WAVEFORM OF WRITE CYCLE NO. 2 (CS CONTROLLED TIMING)(1, 2, 4)
tWC
ADDRESS
CS
R/ W
tAS (6)
tAW
tWP (2)
tWR (7)
tDW
tDH
DATAIN
DATA VALID
2795 drw 08
NOTES:
1. R/W must be HIGH during all address transitions.
2. A write occurs during the overlap (tWP) of a LOW CS and a LOW R/W.
3. tWR is measured from the earlier of CS or R/W (or SEM or R/W) going HIGH to the end of write cycle.
4. During this period, the I/O pins are in the output state and input signals must be applied.
5. If the CS or SEM low transition occurs simultaneously with or after the R/W low transition, the outputs remain in the high impedance state.
6. Timing depends on which enable signal is asserted last.
7. Timing depends on which enable signal is de-asserted first.
8. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to
turn off and data to be placed on the bus for the required tDW. If OE is HIGH during an R/W controlled write cycle, this requirement does
not apply and the write pulse can be as short as the specified tWP.
7.02
7
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