IDT72V3672L10PQF(2003) Ver la hoja de datos (PDF) - Integrated Device Technology
Número de pieza
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Fabricante
IDT72V3672L10PQF Datasheet PDF : 29 Pages
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IDT72V3652/72V3662/72V3672 3.3V CMOS SyncBiFIFOTM
2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
DETERMINING ACTIVE CURRENT CONSUMPTION AND POWER DISSIPATION
The ICC(f) current for the graph in Figure 1 was taken while simultaneously reading and writing a FIFO on the IDT72V3652/72V3662/72V3672 with
CLKA and CLKB set to fS. All data inputs and data outputs change state during each clock cycle to consume the highest supply current. Data outputs were
disconnected to normalize the graph to a zero capacitance load. Once the capacitance load per data-output channel and the number of these device's
inputs driven by TTL HIGH levels are known, the power dissipation can be calculated with the equation below.
CALCULATING POWER DISSIPATION
With ICC(f) taken from Figure 1, the maximum power dissipation (PT) of these FIFOs may be calculated by:
PT = VCC x ICC(f) + Σ(CL x VCC2 X fo)
N
where:
N = number of outputs = 36
CL = outputcapacitanceload
fo = switching frequency of an output
100
90
80
70
60
50
40
30
20
10
0
0
fdata = 1/2 fS
TA = 25°C
CL = 0 pF
10
20
VCC = 3.3V
30
40
50
60
fS Clock Frequency MHz
VCC = 3.6V
VCC = 3.0V
70
80
90
100
4660 drw03a
Figure 1. Typical Characteristics: Supply Current (ICC) vs. Clock Frequency (fS)
7
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