IDT72125 Ver la hoja de datos (PDF) - Integrated Device Technology

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IDT72125

CMOS PARALLEL-TO-SERIAL FIFO 256 x 16, 512 x 16, 1024 x 16

Integrated Device Technology 

IDT72105, IDT72115, IDT72125,

256 x 16, 512 x 16, 1024 x 16 PARALLEL-TO-SERIAL CMOS FIFO

COMMERCIAL TEMPERATURE RANGE

Mode

Inputs

Internal Status

RS

FL

DIR Read Pointer Write Pointer AEF, EF

Reset

Read/Write

0

X

X

Location Zero Location Zero

0

1

X

0,1

Increment(1) Increment(1)

X

NOTE:

1. Pointer will increment if appropriate flag is HIGH.

Table 1. Reset and First Load Truth Table–Single Device Configuration

Outputs

FF

1

X

HF

1

X

2665 tbl 09

The Serial Data Output (SO) of each device in the serial

word must be tied together. Since the SO pin is three stated,

only the device which is currently shifting out is enabled and

driving the 1-bit bus. NOTE: After reset, the level on the

FL/DIR pin decides if the Least Significant or Most Significant

Bit is read first out of each device.

The three flag outputs, Empty (EF), Half-Full (HF) and

Full (FF), should be taken from the Most Significant Device (in

the example, FIFO #2). The Almost-Empty/Almost-Full flag is

not available. The RSOX pin is used for expansion.

PARALLEL DATA IN

SERIAL OUTPUT CLOCK

D 0–15

W

RSIX

LOW AT RESET

SOCP

FL/DIR EF

FIFO #1

HF

RSOX

SO FF

HIGH AT RESET

D 16–31

W

RSIX

SOCP

FL/DIR EF

FIFO #2

HF

RSOX

SO FF

EMPTY FLAG

HALF-FULL FLAG

FULL FLAG

Figure 11. Width Expansion for 32-bit Parallel Data In

SERIAL DATA OUT

2665 drw 14

Depth Expansion (Daisy Chain) Mode

The IDT72105/15/25 can easily be adapted to applications

requiring greater than 1024 words. Figure 12 demonstrates

Depth Expansion using three IDT72105/15/25s and an

IDT74FCT138 Address Decoder. Any depth can be attained

by adding additional devices. The Address Decoder is neces-

sary to determine which FIFO is being written. A word of data

must be written sequentially into each FIFO so that the data

will be read in the correct sequence. The IDT72105/15/25

operates in the Depth Expansion Mode when the following

conditions are met:

1. The first device must be programmed by holding FL LOW

at Reset. All other devices must be programmed by holding

FL HIGH at reset.

2. The Read Serial Out Expansion pin (RSOX) of each device

must be tied to the Read Serial In Expansion pin (RSIX) of

the next device (see Figure 12).

3. External logic is needed to generate composite Empty,

Half-Full and Full Flags. This requires the OR-ing of all EF,

HF and FF Flags.

4. The Almost-Empty and Almost-Full Flag is not available

due to using the RSOX pin for expansion.

Compound Expansion (Daisy Chain) Mode

The IDT72105/15/25 can be expanded in both depth and

width as Figure 13 indicates:

1. The RSOX-to-RSIX expansion signals are wrapped

around sequentially.

2. The write (W) signal is expanded in width.

3. Flag signals are only taken from the Most Significant

Devices.

4. The Least Significant Device in the array must be

programmed with a LOW on FL/DIR during reset.

5.35

9

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