IDT71V3559SA75PFI Ver la hoja de datos (PDF) - Integrated Device Technology

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IDT71V3559SA75PFI

128K x 36, 256K x 18, 3.3V Synchronous ZBT™ SRAMs 3.3V I/O, Burst Counter, Flow-Through Outputs

Integrated Device Technology 

IDT71V3557, IDT71V3559, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

ZBT™ Feature, 3.3V I/O, Burst Counter, and Flow-Through Outputs

Commercial and Industrial Temperature Ranges

Pin Configuration — 128K x 36, 165 fBGA

1

2

3

4

5

6

7

8

9

10

11

A

NC(3)

A7

CE1

BW3

BW2

CE2

CEN

ADV/LD

NC(3)

A8

NC

B

NC

A6

CE2

BW4

BW1

CLK

R/W

OE

NC(3)

A9

NC(3)

C

I/OP3

NC

VDDQ

VSS

VSS

VSS

VSS

VSS

VDDQ

NC

I/OP2

D

I/O17

I/O16

VDDQ

VDD

VSS

VSS

VSS

VDD

VDDQ

I/O15

I/O14

E

I/O19

I/O18

VDDQ

VDD

VSS

VSS

VSS

VDD

VDDQ

I/O13

I/O12

F

I/O21

I/O20

VDDQ

VDD

VSS

VSS

VSS

VDD

VDDQ

I/O11

I/O10

G

I/O23

I/O22

VDDQ

VDD

VSS

VSS

VSS

VDD

VDDQ

I/O9

I/O8

H

VSS(1)

VDD(2)

NC

VDD

VSS

VSS

VSS

VDD

NC

NC

NC/ZZ(6)

J

I/O25

I/O24

VDDQ

VDD

VSS

VSS

VSS

VDD

VDDQ

I/O7

I/O6

K

I/O27

I/O26

VDDQ

VDD

VSS

VSS

VSS

VDD

VDDQ

I/O5

I/O4

L

I/O29

I/O28

VDDQ

VDD

VSS

VSS

VSS

VDD

VDDQ

I/O3

I/O2

M

I/O31

I/O30

VDDQ

VDD

VSS

VSS

VSS

VDD

VDDQ

I/O1

I/O0

N

I/OP4

NC

VDDQ

VSS

NC/ TRST(4, 5)

NC

VSS(1)

VSS

VDDQ

NC

I/OP1

P

NC

NC(3)

A5

A2

NC/TDI(4)

A1

NC/TDO(4)

A10

A13

A14

NC

R

LBO

NC(3)

A4

A3

NC/TMS ( 4)

A0

NC/TCK(4)

A11

A12

A15

A16

5282 tbl 25

Pin Configuration - 256K x 18, 165 fBGA

1

2

3

4

5

6

7

8

9

10

11

A

NC(3)

A7

CE1

BW2

NC

CE2

CEN

ADV/LD

NC(3)

A8

A10

B

NC

A6

CE2

NC

BW1

CLK

R/W

OE

NC(3)

A9

NC(3)

C

NC

NC

VDDQ

VSS

VSS

VSS

VSS

VSS

VDDQ

NC

I/OP1

D

NC

I/O8

VDDQ

VDD

VSS

VSS

VSS

VDD

VDDQ

NC

I/O7

E

NC

I/O9

VDDQ

VDD

VSS

VSS

VSS

VDD

VDDQ

NC

I/O6

F

NC

I/O10

VDDQ

VDD

VSS

VSS

VSS

VDD

VDDQ

NC

I/O5

G

NC

I/O11

VDDQ

VDD

VSS

VSS

VSS

VDD

VDDQ

NC

I/O4

H

Vss ( 1)

VDD(2)

NC

VDD

VSS

VSS

VSS

VDD

NC

NC

NC/ZZ(6)

J

I/O12

NC

VDDQ

VDD

VSS

VSS

VSS

VDD

VDDQ

I/O3

NC

K

I/O13

NC

VDDQ

VDD

VSS

VSS

VSS

VDD

VDDQ

I/O2

NC

L

I/O14

NC

VDDQ

VDD

VSS

VSS

VSS

VDD

VDDQ

I/O1

NC

M

I/O15

NC

VDDQ

VDD

VSS

VSS

VSS

VDD

VDDQ

I/O0

NC

N

I/OP2

NC

VDDQ

VSS

NC/ TRST(4, 5)

NC

VSS(1)

VSS

VDDQ

NC

NC

P

NC

NC(3)

A5

A2

NC/TDI(4)

A1

NC/TDO(4)

A11

A14

A15

NC

R

LBO

NC(3)

A4

A3

NC/TMS(4)

A0

NC/TCK(4)

A12

A13

A16

A17

5282 tbl 25a

NOTES:

1. H1 and N7 do not have to be directly connected to VSS as long as the input voltage is < VIL.

2. H2 does not have to be directly connected directly to VDD as long as the input voltage is ≥ VIH.

3. A9, B9, B11, A1, R2, and P2 are reserved for future 9M, 18M, 36M, 72M, 144M, and 288M respectively.

4. These pins are NC for the "S" version and the JTAG signal listed for the "SA" version.

5. TRST is offered as an optional JTAG reset if requested in the application. If not needed, can be left floating and will internally be pulled to VDD.

6. Pin H11 supports ZZ (sleep mode) for the latest die revisions.

6.482

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