IDT71V3557SA80BQI Ver la hoja de datos (PDF) - Integrated Device Technology
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Fabricante
IDT71V3557SA80BQI
Integrated Device Technology
IDT71V3557SA80BQI Datasheet PDF : 28 Pages
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IDT71V3557, IDT71V3559, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
ZBT™ Feature, 3.3V I/O, Burst Counter, and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
Device Operation - Showing Mixed Load, Burst,
Deselect and NOOP Cycles (2)
Cycle
Address
R/W ADV/LD CE1(1) CEN BWx
OE
I/O Comments
n
A0
H
L
L
L
X
X
D1 Load read
n+1
X
X
H
X
L
X
L
Q0 Burst read
n+2
A1
H
L
L
L
X
L
Q0+1 Load read
n+3
X
X
L
H
L
X
L
Q1 Deselect or STOP
n+4
X
X
H
X
L
X
X
Z NOOP
n+5
A2
H
L
L
L
X
X
Z Load read
n+6
X
X
H
X
L
X
L
Q2 Burst read
n+7
X
X
L
H
L
X
L
Q2+1 Deselect or STOP
n+8
A3
L
L
L
L
L
X
Z Load write
n+9
X
X
H
X
L
L
X
D3 Burst write
n+10
A4
L
L
L
L
L
X
D3+1 Load write
n+11
X
X
L
H
L
X
X
D4 Deselect or STOP
n+12
X
X
H
X
L
X
X
Z NOOP
n+13
A5
L
L
L
L
L
X
Z Load write
n+14
A6
H
L
L
L
X
X
D5 Load read
n+15
A7
L
L
L
L
L
L
Q6 Load write
n+16
X
X
H
X
L
L
X
D7 Burst write
n+17
A8
H
L
L
L
X
X
D7+1 Load read
n+18
X
X
H
X
L
X
L
Q8 Burst read
n+19
A9
L
L
L
L
L
L
Q8+1 Load write
NOTES:
1. CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals.
2. H = High; L = Low; X = Don't Care; Z = High Impedence.
5282 tbl 12
6.1412
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