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IDT71028S12Y

CMOS Static RAM 1 Meg (256K x 4-Bit)

Integrated Device Technology 

IDT71028 CMOS Static RAM

1 Meg (256K x 4-Bit)

Timing Waveform of Read Cycle No. 1(1)

ADDRESS

tRC

tAA

OE

CS

DATAOUT

tOE

tOLZ (5)

tCLZ (5)

tACS (3)

HIGH IMPEDANCE

tPU

VCC SUPPLY ICC

CURRENT ISB

Commercial and Industrial Temperature Ranges

tOHZ (5)

tCHZ (5)

DATAOUT VALID

tPD

2966 drw 05

Timing Waveform of Read Cycle No. 2(1,2,4)

ADDRESS

DATAOUT

tRC

tAA

tOH

PREVIOUS DATAOUT VALID

NOTES:

1. WE is HIGH for Read Cycle.

2. Device is continuously selected, CS is LOW.

3. Address must be valid prior to or coincident with the later of CS transition LOW; otherwise tAA is the limiting parameter.

4. OEis LOW.

5. Transition is measured ±200mV from steady state.

tOH

DATAOUT VALID

2966 drw 06

6.452

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