IDT70V657S(2008) Ver la hoja de datos (PDF) - Integrated Device Technology
Número de pieza
componentes Descripción
Fabricante
IDT70V657S
(Rev.:2008)
(Rev.:2008)
Integrated Device Technology
IDT70V657S Datasheet PDF : 24 Pages
| |||
HIGH-SPEED 3.3V
128/64/32K x 36
IDT70V659/58/57S
ASYNCHRONOUS DUAL-PORT
STATIC RAM
Features
◆ True Dual-Port memory cells which allow simultaneous
access of the same memory location
◆ High-speed access
– Commercial: 10/12/15ns (max.)
– Industrial: 12/15ns (max.)
◆ Dual chip enables allow for depth expansion without
external logic
◆ IDT70V659/58/57 easily expands data bus width to 72 bits
or more using the Master/Slave select when cascading
more than one device
◆ M/S = VIH for BUSY output flag on Master,
M/S = VIL for BUSY input on Slave
◆ Busy and Interrupt Flags
◆ On-chip port arbitration logic
◆ Full on-chip hardware support of semaphore signaling
between ports
◆ Fully asynchronous operation from either port
◆ Separate byte controls for multiplexed bus and bus
matching compatibility
◆ Supports JTAG features compliant to IEEE 1149.1
◆ LVTTL-compatible, single 3.3V (±150mV) power supply for
core
◆ LVTTL-compatible, selectable 3.3V (±150mV)/2.5V (±100mV)
power supply for I/Os and control signals on each port
◆ Available in a 208-pin Plastic Quad Flatpack, 208-ball fine
pitch Ball Grid Array, and 256-ball Ball Grid Array
◆ Industrial temperature range (–40°C to +85°C) is available
for selected speeds
◆ Green parts available, see ordering information
Functional Block Diagram
BE3L
BE3R
BE2L
BE2R
BE1L
BE0L
BE1R
BE0R
R/WL
CE0L
CE1L
B BBB BBBB
E EEE EEEE
0 123 3210
L L L L RRRR
R/W R
CE0R
CE1R
OEL
I/O0L- I/O35L
Dout0-8_L
Dout0-8_R
Dout9-17_L Dout9-17_R
Dout18-26_L Dout18-26_R
Dout27-35_L Dout27-35_R
128/64/32K x 36
MEMORY
ARRAY
Di n_L
Di n_R
OER
I/O0R -I/O35R
A16 L(1)
A0L
Address
Decoder
ADDR_L
ADDR_R
BUSYL(2,3)
SEML
INTL(3)
CE0L
CE1L
OEL
R/WL
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
M/S
TDI
TDO
JTAG
NOTES:
1. A16 is a NC for IDT70V658. Also, Addresses A16 and A15 are NC's for IDT70V657.
2. BUSY is an input as a Slave (M/S=VIL) and an output when it is a Master (M/S=VIH).
3. BUSY and INT are non-tri-state totem-pole outputs (push-pull).
1
©2008 Integrated Device Technology, Inc.
Address
Decoder
OER
R/WR
CE0R
CE1R
TMS
TCK
TRST
A16R(1)
A0R
BUSYR(2,3)
SEMR
INTR(3)
4869 drw 01
OCTOBER 2008
DSC-4869/7
Share Link: