IDT70V659S(2008) Ver la hoja de datos (PDF) - Integrated Device Technology

Número de pieza

componentes Descripción

Fabricante

IDT70V659S
(Rev.:2008)

HIGH-SPEED 3.3V 128/64/32K x 36 ASYNCHRONOUS DUAL-PORT STATIC RAM

Integrated Device Technology 

IDT70V659/58/57S

High-Speed 3.3V 128/64/32K x 36 Asynchronous Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

DC Electrical Characteristics Over the Operating

Temperature and Supply Voltage Range (VDD = 3.3V ± 150mV)

70V659/58/57S

Symbol

Parameter

Test Conditions

Min.

Max. Unit

|ILI|

Input Leakage Current(1)

VDDQ = Max., VIN = 0V to VDDQ

___

10

µA

|ILO|

Output Leakage Current

VOL (3.3V) Output Low Voltage(2)

CE0 = VIH or CE1 = VIL, VOUT = 0V to VDDQ

IOL = +4mA, VDDQ = Min.

___

10

µA

___

0.4

V

VOH (3.3V) Output High Voltage(2)

VOL (2.5V) Output Low Voltage(2)

IOH = -4mA, VDDQ = Min.

IOL = +2mA, VDDQ = Min.

2.4

___

V

___

0.4

V

VOH (2.5V) Output High Voltage(2)

IOH = -2mA, VDDQ = Min.

2.0

___

V

NOTE:

1. At VDD < - 2.0V input leakages are undefined.

2. VDDQ is selectable (3.3V/2.5V) via OPT pins. Refer to p.6 for details.

4869 tbl 09

DC Electrical Characteristics Over the Operating

Temperature and Supply Voltage Range(3) (VDD = 3.3V ± 150mV)

70V659/58/57S10 70V659/58/57S12 70V659/58/57S15

Com'l Only

Com'l

Com'l

& Ind

& Ind

Symbol

Parameter

Test Condition

Version

Typ.(4) Max. Typ.(4) Max. Typ.(4) Max. Unit

IDD Dynamic Operating CEL and CER= VIL,

Current (Both

Outputs Disabled

Ports Active)

f = fMAX(1)

COM'L S 340

500

315

465

300

440 mA

IND

S

____

____

365

515

350

490

ISB1 Standby Current

(Both Ports - TTL

Level Inputs)

CEL = CER = VIH

f = fMAX(1)

COM'L S 115

165

90

125

75

100 mA

IND

S

____

____

115

150

100

125

ISB2 Standby Current

(One Port - TTL

Level Inputs)

CE"A" = VIL and CE"B" = VIH(5)

Active Port Outputs Disabled,

f=fMAX(1)

COM'L S 225

340

200

325

175

315 mA

IND

S

____

____

225

365

200

350

ISB3 Full Standby Current Both Ports CEL and

(Both Ports - CMOS CER > VDDQ - 0.2V,

COM'L S 3

15

3

15

3

15 mA

Level Inputs)

VIN > VDDQ - 0.2V or VIN < 0.2V,

f = 0(2)

IND

S

____

____

6

15

6

15

ISB4 Full Standby Current CE"A" < 0.2V and

(One Port - CMOS CE"B" > VDDQ - 0.2V(5)

Level Inputs)

VIN > VDDQ - 0.2V or VIN < 0.2V,

Active Port, Outputs Disabled,

f = fMAX(1)

mA

COM'L S 220

335

195

320

170

310

IND

S

____

____

220

360

195

345

NOTES:

4869 tbl 10

1. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC, using "AC TEST CONDITIONS" at input

levels of GND to 3V.

2. f = 0 means no address or control lines change. Applies only to input at CMOS level standby.

3. Port "A" may be either left or right port. Port "B" is the opposite from port "A".

4. VDD = 3.3V, TA = 25°C for Typ, and are not production tested. IDD DC(f=0) = 120mA (Typ).

5. CEX = VIL means CE0X = VIL and CE1X = VIH

CEX = VIH means CE0X = VIH or CE1X = VIL

CEX < 0.2V means CE0X < 0.2V and CE1X > VDDQ - 0.2V

CEX > VDDQ - 0.2V means CE0X > VDDQ - 0.2V or CE1X - 0.2V

"X" represents "L" for left port or "R" for right port.

9

Share Link: